What causes SMPS voltage ripple?

Question

In many datasheets and application guides there is always an equation for ripple current, because it is fundamental to the operation of a buck or boost converter, but I never see a direct equation for ripple voltage.

I know the ripple comes from the finite capacitance that needs to discharge the load current during the off-part of the duty cycle, so I suspect the equation is a second order (since the derivative of the capacitors voltage depends on the derivative of the inductor current). I also know the capacitor’s ESR plays a role.

I ask out of experience. Once I built a boost converter and the output voltage ripple grew to over 100mV at max load, whereas another time I build a boost converter and the ripple was constant at 4mV across all loads. These were clearly satisfying very different power requirements, but what is the interplay between capacitance ESR and the pure inductive/capacitance relationship in determining output ripple? And when does it start to vary significantly across loads?

Answer 1

I suspect the equation is a second order (since the derivative of the capacitors voltage depends on the derivative of the inductor current)

This is fundamental to understanding the ripple voltage. The inductor and capacitor form a 2nd order low-pass filter with an input that can be assumed to be a square wave of variable duty cycle to accomodate load and incoming supply variations.

Given that the inductor and capacitor have a natural resonance significantly below the switching frequency (maybe at one tenth) you can expect that the 1st fundamental of the square wave to be attenuated by 40 dB because a 2nd order low-pass filter attenuates at 40 dB per decade.

So if the square wave (switching waveform) was 12 volts p-p then the fundamental would be reduced by 40 dB to 120 mV p-p and the harmonics reduced even more.

If the switching frequency is 100 times the LC natural frequency then the 12 volts p-p is attenuated by 80 dB to 1.2 mV p-p. However, there is a trade-off - to obtain maximum dynamic control when dealing with load current variations, it is desirable to have the LC natural frequency as high as possible so it's a compromise.

With capacitive ESR the attenuation of the LC filter will not continue at 40 dB/decade but will eventually turn into 20 dB/decade as the LC becomes an LR single order low-pass filter.

Answer 2

Quite likely all the discrete and the parasitic Cs and Ls interact, and cause ripple/ringing. Thus you should expect "ripple" at 150MHz because of 10nH (0.010uH) interacting with 100pF Cout of onchip power FETs.

And all other possible LC resonators may be a problem, depending upon the amount of resistive dampening in the energy-circulation loop.

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By the way, ANY closed path, any loop, with inductors and capacitors in series, will be resonant.

Whether you see any ringing will depend on

• the impulsive energy available to trigger ringing

• the losses inside the loop, that dampen ringing

• the ratio of the impulsive edge or step (often just a few nanoseconds, on silicon), to the period of ringing;

• (a) if the edge is much slower than the ringing period, expect little or no ringing;

• (b) if the edge is exactly the period of the ringing, then you might see NO ringing in the real PCB/IC because of how the resonant system integrates the incoming energy over a full cycle

• (b') this is what causes nulls in sin(x)/x responses

• if the edge is much faster than the ringing period, expect LOTS of ringing, because a STEP FUNCTION is standard method of forcing a system to display its "natural response" which for our Loops is the resonant ringing