# vhdl generate multiple range

I have 2 checks which are similar, except by the range of the generate: All works OK, it looks like this:

check : for bit in (1 to 5)  generate
process
some cool stuff;
end process;
end generate  check ;

check2 : for bit in (7 to 8)  generate
process
Same some cool stuff;
end process;
end generate  check2 ;


I would like to implement something simpler to maintain like this:

check : for bit in (1 to 5) & (7 to 8)  generate
process
Simpler to mantain the cool stuff;
end process;
end generate  check ;


Is this possible ??

• In this case you could do a range of 1 to 8 and add an if not 6 – Oldfart Jul 24 '18 at 10:30
• No. A for generate parameter specification is a single discrete range. A range consists of scalar bounds and a direction. – user8352 Jul 24 '18 at 11:17
• Question apart, 'BIT' is datatype keyword ... So it can't be used as indexing for generate I guess. – Sourabh Tapas Jul 29 '18 at 5:09
• The 'bit' parent byte/word etc must be named first. Bit cans must be named. – Sparky256 Aug 2 '18 at 0:11

You can define your range as an array and use the for-loop to run through this array:

type arr is array(0 to 7) of integer;
constant bit : arr := (0,1,2,3,4,5,7,8);

[..]
check : for i in 0 to 7 generate
cool_stuff(bit(i));
end generate;


i followed the "oldfart" user sugestion , and did a range 1 to 8 and added an if not for 6...

There probably cleaner ways to do it , but it works..

i'm still interested in cleaner ways...