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I would like to simulate a verilog design that is to interface (via a FiFo to USB chip) with a program running on my computer. I have set up my program to redirect all reads and writes to Linux FiFo files (man mkfifo) and am now trying to write a testbench for my verilog code that emulates the FiFo to USB chip. The idea is to read data from the Linux FiFo file and -if there is any- forward it to my DUT.

The Verilog standard names a number of system tasks to read data from a file

  • $fgetc (Get a byte)
  • $fgets (Get a string)
  • $fscanf (Get formatted data)
  • $fread (Get binary data)
  • $readmem* (Fill a whole memory at once)

However, these system tasks will block until there is data available or an error occurs. Even worse, they block the whole testbench even when fork'ed so something along the lines of

reg [8:0] code = 9'd0;
...
fork : fgetc_with_timeout
    begin
        code=$fgetc(input_file);
        disable fgetc_with_timeout;
    end
    begin
        #300;
        disable fgetc_with_timeout;
    end
join
if(code)
...

will not work. So, is there any way to get a nonblocking read from a file or is there a way to get the number of remaining bytes/bits/words in a file?

I am using Xilinx ISE so I am constrained to Verilog (not System Verilog), so I am looking for something that works in ISE, and I would prefer to not use PLI code for this if possible.

Best regards, mox

p.S.> Searching for anything involving 'nonblocking' and 'verilog' lists mostly results not related to my problem, however I have found this non-answered question at the Xilinx forums: https://forums.xilinx.com/t5/Simulation-and-Verification/xsim-and-Verilog-file-IO-is-non-blocking-read-of-a-file-possible/td-p/685611

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    \$\begingroup\$ You may need to set the file involved to a non-blocking mode with OS calls snuck in around the edge somehow. In the end it might be simpler to use VPI and a little custom C program to feed this in - remember it's not enough to get data or not get data, you need to signal if the simulated FIFO has something or not. \$\endgroup\$ – Chris Stratton Jul 24 '18 at 14:18
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This cannot be done in Verilog alone. You are trying to mix a real-time system with a simulation-time system. You need to write a Verilog model that emulates the behavior of the FIFO output with random times for putting out data.

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This is an application for PLI or other cosimulation interface. In general, this is a binary interface where you write a shared object in C and then the simulator will load it and interact with it.

If you can run your Verilog design in Icarus Verilog, then you can use MyHDL to drive the top level and interface with the outside world via python.

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