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What is the typical area taken by address decoder logic in a SRAM? Could someone post area breakdown for each components in a SRAM?

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This is the die of an Intel 3101 Static RAM chip, as annotated by Ken Shirriff:

3101 die photo

This is a 4-bit wide x 16 bipolar static RAM, which means it's simple enough that you can see all the components and understand everything in it at the same time.

Modern RAM chips, of course, have more address bits, which makes their address decode circuitry more complex, but also tend to have more data bits, which has a tendency to counteract that. Therefore the split between these two components is, at least to a first approximation, similar to what it was in the 3101.

The one major difference is that the driver circuits and the sense amplifiers are much smaller in relation to the storage/decode area on a modern chip.

For more detailed analysis of how the 3101 works, see the blog entry I got this image from.

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