I'm using a LQFP-64 MCU on a 2 layer board (ground plane plus power/signal plane), and I'm trying very hard to avoid running traces on the ground plane. Some of them can be routed out the corners of the MCU. I do have a couple problematic traces, and my solution is route the traces back under the MCU and out other pins. I'll configure the "secondary" pins as digital inputs to avoid double driving the signal.

  1. Is this a bad idea? I guess there's extra parasitic capacitance. FWIW the signals are <=1MHz, probably <=125kHz. I need to check that the bootloader and reset states don't drive the pins, but otherwise it seems just fine?

  2. Will EMC be a problem? I have an unbroken ground plane on the far side from the MCU, but there won't be a solid power plane directly under the MCU. The MCU itself will probably run around 12MHz, maybe 24-48MHz.

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    \$\begingroup\$ What you are doing is unusual. I would try pretty hard NOT to do it. Subject to the issues you already thought of, it should work, but... \$\endgroup\$ – mkeith Jul 25 '18 at 3:44
  • \$\begingroup\$ Hopefully you got a 4 layer design, 2 signal layers, a gnd plane and a VCC plane. Using only 2 layers will be very hard to impossible. \$\endgroup\$ – Uwe Jul 25 '18 at 10:57
  • \$\begingroup\$ @Uwe "I'm using a LQFP-64 MCU on a 2 layer board" \$\endgroup\$ – Maple Jul 25 '18 at 11:08

I've done this before, and it does require some precautions that you set those pins to inputs on the MCU. Other than that, most MCU pins can withstand short circuit for a short while.. so I think it is survivable if you set them up incorrectly during development.

Alternatively what you could do, is add soldermask to the pads that you use for snaking traces like this. That way the QFP pin doesn't get soldered to the board.

However, not sure how well this trick will hold up if you plan on mass producing the board.

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  • \$\begingroup\$ Should those "route through" pins be floating inputs or inputs with internal pullup/pulldown? \$\endgroup\$ – George Aug 4 '19 at 17:20

As @mkeith answered in comments, in theory this should work, but

  • This has huge potential for "Oops..." kind of magic smoke situations during development, especially if you decide to modify code years later.
  • You might be fighting imaginary or self-created problem here. If "there won't be a solid power plane directly under the MCU" anyway, then why not use it to bring couple traces just from under the MCU?
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  • \$\begingroup\$ When I said there won't be a solid power plane, I mean the top layer won't have an unbroken 5V pour right below the MCU. However, the ground plane / bottom layer will have an unbroken pour. So yes, I do intend to use the top layer to route the pin signals under the MCU, and then out another pin. \$\endgroup\$ – CarCircuits Jul 25 '18 at 16:21
  • \$\begingroup\$ Yes, I've re-read your question and I see what you mean. Still don't get why. If this is not high frequency application couple very short traces on the ground plane will not have negative effects, and will have two positive - simplified routing and no potential shorts. \$\endgroup\$ – Maple Jul 25 '18 at 18:04
  • \$\begingroup\$ Routing would be more complicated - I need vias to hop planes, and the fab I'm using has larger vias than traces, so I need to make room for the vias. Also, I'm not worried about the potential for shorts. That possibility exists for any MCU input (such as CAN or UART rx) where the MCU can drive a pin that is also driven by an external IC. \$\endgroup\$ – CarCircuits Jul 25 '18 at 18:48
  • \$\begingroup\$ Don't actually short the pins. The very tiny source-drain spacing of modern CMOS makes for excellent drive strength (High GM) and also for very tiny thermal mass thus very rapid heating --- how about a Million degrees per microsecond. \$\endgroup\$ – analogsystemsrf Jul 26 '18 at 4:45

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