# Background

I'm looking at the RF (LNA_IN) pin of ESP32 as described in esp32_hardware_design_guidelines.

According to this document, the output impedance of the RF pins of ESP32 are (30+j10) or (35+j10) Ω (depends on package), while the antenna impedance is expected to be 50Ω.
It suggests the following π-type matching network: Now I would like to model (simulate) this circuit to test the impedance matching.

### Question 1

To simulate the source output impedance I've added a 30Ω resistor in series to the source. But what would be the best way to model the imaginary part j10?

### Question 2

To simulate the antenna impedance I've added a 50Ω resistor. Let's say this is a 50Ω MIFA pcb trace antenna like this one. Does such antenna have an imaginary impedance part and how do I model it?

So I tried this: simulate this circuit – Schematic created using CircuitLab

Simulating DB(MAG( (V(Out) * I(R1.nA)) / (I(I1.nA) * V(In)) )) on frequency domain: ### Question 3

At first glance it more-or-less makes sense (-0.3dB on 2.4Ghz). What puzzles me is that the result of the simulation is independent of the source impedance value. For example, here I tried to sweep R2 from 0Ω to 100Ω. The graph below looks the same for every value of R2. What am I missing here? Here is another implementation for the impedance matching circuit I found in another design, probably a "tapped capacitor" matching: simulate this circuit

Here, a nice 0dB peak on 2.4Ghz, but when sweeping the value of R2 the result remains the same, independent from R2 resistance. So Question 3 applies here too: ### Question 4

In general, what would be the considerations for selecting either the π-type or the "tapped capacitor" matching network? The simulation graphs look quite different, I wonder what works best from practical aspects.

• Monopole-type antennas, like a wavy track at the edge of the PCB, often have impedance well below 50 Ohms at resonance. Consider using a simple 30 Ohm track and no matching? Also, the loss in potential output power from 30 to 50 is very small... Jul 26, 2018 at 4:37

(30+j10) is indicating that the pin has some inductance associated with it. J10 is the inductive reactance at a given frequency. Since no frequency is specified, lets assume it is the operating frequency of 2.4 GHz which gives an inductance of 663 pH.

Your simulation is plotting the power ratio of out/in. This does not include R2 and so is independent of R2. If you move the node labeled In to I1 then you will see an effect of R2.

At these frequencies the parasitic elements of capacitors and inductors are significant, so it would be a good idea to find out what they are and include them in the simulation, or find a spice model for them.

1: what is inductance for j10 at 2.4GHz?

$L=Z_L/2\pi f =$ ~ 0.66 nH or about a wire length 1 mm thick depending on layout.

I am assuming you can transform a 50 Ohms generator down to 30 Ohms !

2: Your transform excludes R1 since Vin is after R1 from V1

3: same as 2:

4: Tapped C is a 2nd order BPF
while Pi is a 3rd order LPF .

Depends on harmonic attenuation needs.