I'm looking at the RF (LNA_IN) pin of ESP32 as described in esp32_hardware_design_guidelines.
According to this document, the output impedance of the RF pins of ESP32 are (30+j10) or (35+j10) Ω (depends on package), while the antenna impedance is expected to be 50Ω.
It suggests the following π-type matching network:
Now I would like to model (simulate) this circuit to test the impedance matching.
To simulate the source output impedance I've added a 30Ω resistor in series to the source. But what would be the best way to model the imaginary part j10?
To simulate the antenna impedance I've added a 50Ω resistor. Let's say this is a 50Ω MIFA pcb trace antenna like this one. Does such antenna have an imaginary impedance part and how do I model it?
So I tried this:
DB(MAG( (V(Out) * I(R1.nA)) / (I(I1.nA) * V(In)) )) on frequency domain:
At first glance it more-or-less makes sense (-0.3dB on 2.4Ghz). What puzzles me is that the result of the simulation is independent of the source impedance value. For example, here I tried to sweep R2 from 0Ω to 100Ω. The graph below looks the same for every value of R2. What am I missing here?
Here is another implementation for the impedance matching circuit I found in another design, probably a "tapped capacitor" matching:
In general, what would be the considerations for selecting either the π-type or the "tapped capacitor" matching network? The simulation graphs look quite different, I wonder what works best from practical aspects.