Opamp current source stable in simulation but unstable on prototype

Question

I've tried to build this opamp/mosfet current source, and been struggling to make it stable. When simulating the open-loop gain in PSpice. I've set it up like this, which should give Vout = -AB at the output of the opamp.

^{simulate this circuit – Schematic created using CircuitLab}

And it looks to have a huge phase margin on the plot:

Which also shows if I step the input with a 1 ns rise pulse, that it is very stable(measured at the output of the opamp):

But unfortunately it is very unstable on the prototype PCB that I made. The first picture is when the input voltage is 0, or below 10 mV. The second picture is when I increase the voltage to around 70 mV at the input:

Here is a picture of the PCB:

I could not route the 5 V for the opamp on the single sided PCB, so I made a small jumper. At the input of the 5 V there is a 10 µF electrolytic and a 100 nF ceramic as a bypass.

The green wire at the bottom is the input to the opamp. The other green wire is measurement at the gate of the opamp.

How can I simulate this circuit correctly?

How can I stop the oscillations in my circuit?

EDIT: I forgot to mention that I added C2 because the mosfet I'm using (ST P36NE06) has more input capacitance than this BUZ11 FET has.

Answer 1

The problem is the loop has not been compensated correctly, it wants to oscillate as shown your graph on the red scope trace (the voltage probe) I have a similar plot below:

This can also be seen in the closed loop gain (green trace) the hill at 10Mhz indicates that there is a Q point that wants to ring around 10Mhz (but why not 1Mhz like the design resonates at? stay tuned).

So how to fix this? Use a lot more capacitance, 10uF and move it to the other side of the resistor. After doing so you get the red trace, which shows very little ringing.

There are a few other caveats, there has been no parasitics simulated! So either build your design as close as possible to the schematic OR simulate the parasitics by estimating them from the board. Part of the reason for the simulation showing a resonance point at 10Mhz and the design at 1Mhz is parasitic inductance has not been simulated.

Cables will contribute 10nH's, the traces can also have some inductance and resistance. I could go into much detail but have ran out of time. The way to calculate this is with trace inductance/resistance calculators.

In these kind of circuits inductance can change things, where it normally can be neglected. You may also want to include the source resistance of the wire and the simulation as the current source and the power filter caps can also contribute to resonance.

Answer 2

The main problem that I see is that your open loop simulation isolates the op-amp output from the gate-source capacitance with a 1 giga henry inductor. This naturally does the job of maintaining DC conditions around the loop but, and very importantly, fails to take into account how susceptible the AD8616 is to capacitive loads on the output.

For instance, if you look at figure 17 in the data sheet you can see that you are going to get "indecent" levels of overshoot with 1nF + gate-source capacitance (1.5 nF). Added to this is figure 14 and this tells you how the output impedance of the op-amp varies with frequency for certain gain levels. Your op-amp gain is practically as high as it gets (no local feedback) so you can assume the output resistance will be about 30 ohms or maybe mush more in the frequencies of interest.

Again, in your sim, this impedance is buffered by the 1 giga henry inductor and this means that your sim will not take this into account.

Circa 60 ohms output resistance and 2.5 nF has a 3dB point of about 1 MHz and adds a whopping 45 degrees to the open-loop phase shift. Note also these words in the data sheet: -

That is probably the last nail in the coffin.