I'm trying to get an ESP8266 to wake up via external trigger. The trigger in this case is a PIR, which sends a 2+ second high signal when motion is detected.

I'm using an edge detector to turn that incoming long signal into a brief signal, and then inverting it via transistor as the ESP needs to have the RST pin grounded for a brief second to cause a boot.

This is the simplest form of the circuit:

enter image description here

The issue I'm having is the voltage drop on RST is not low enough. There used to be a pull-up resistor on RST when I played with a NodeMCU, but now with a Wemos D1 mini the voltage drop wasn't high enough to trigger a boot.

With the Wemos plugged into USB and providing power to everything, the circuit runs at 3.3v and RST drops to around 2v on trigger, which is enough to cause a boot most of the time, but ideally I want to get the drop lower still. Any ideas on that?

The real problem comes in when this setup is connected to a 3.7v battery. When the battery is full, everything gets around 4.2v and on trigger, the drop on RST is only down to 2.6v which is no where near what's needed to trigger a boot.

How can I get a trigger to cause a larger drop on RST? Not longer though - just a larger drop. Increasing C1 to 10uF does increase the drop, but the time it takes is too long.

Also, as the battery drains, the voltage will drop over time. I need a solution that works at 4.2v all the way down to 2.7v (at which time there likely won't be enough juice to start the ESP anyway).

In case it's relevant, Q2 is a 2N222.

  • \$\begingroup\$ Can you show source impedance and signal? Use CMOS inverter instead. \$\endgroup\$ Jul 26, 2018 at 21:59
  • \$\begingroup\$ Or define PIR part number \$\endgroup\$ Jul 26, 2018 at 22:05
  • \$\begingroup\$ The PIR is a AM312 (banggood.com/…) \$\endgroup\$ Jul 27, 2018 at 12:58
  • \$\begingroup\$ AM312 can provide logic levels out same as Vdd and Vss but max current output is 10mA. So edge detection can be done by low level logic gate and time delay such as FF Clk and FF Reset delayed by 1mA or input delayed 1ms inverted AND input =1ms pulse \$\endgroup\$ Jul 27, 2018 at 14:44
  • 1
    \$\begingroup\$ Your pullup load seems to be too much. What is it? The impedance can be raised to 100k so collector can pull down to 0.5V C1 can be reduced to 10ms or 10nF \$\endgroup\$ Jul 27, 2018 at 15:10

1 Answer 1



simulate this circuit – Schematic created using CircuitLab

Replace Q2 with an N channel, enhancement mode MOSFET with a low "on" resistance and a gate threshold voltage around one volt. This will pull you all the way to ground.

  • \$\begingroup\$ I tried a RFP30N06LE mosfet (only n-channel I have lying around) and nothing happens with that at all :-( \$\endgroup\$ Jul 27, 2018 at 13:00
  • \$\begingroup\$ Good enough choice on the part. You installed it as shown? What is the rise time on your edge? \$\endgroup\$ Jul 27, 2018 at 13:52
  • \$\begingroup\$ Yes, that's how I installed it. RST is reading 3.8v and when the PIR triggers, I'm lucky to get a dip down to 3.7v. With the 2N222 I at least get a dip to 2.6v. Nothing else in the circuit has changed. \$\endgroup\$ Jul 27, 2018 at 14:04
  • \$\begingroup\$ What is the peak gate voltage? \$\endgroup\$ Jul 27, 2018 at 14:14
  • 1
    \$\begingroup\$ RFP30N06LE has a VGS (th) maximum of 2 volts and they define VGS(th) as the place where you get 250 ua of drain current, so you are right on the edge. You would need one that has a lower VGS(th). If you want to use parts on hand, you could try swapping the emitter and collector on the 2n2222. The beta is much lower in this mode, but the VCE(sat) voltage will be lower too. We used to do this to dump sample-and-hold circuits in the pre-FET days. \$\endgroup\$ Jul 27, 2018 at 14:54

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service and acknowledge that you have read and understand our privacy policy and code of conduct.

Not the answer you're looking for? Browse other questions tagged or ask your own question.