In previous designs, I have used an MCU digital output to drive the lower side of a resistor ladder to the supply voltage, to prevent power consumption when the ladder is not being sampled:
This led me to wonder (in the schematic below):
If the MCU supply (VCC) was 3.3V, and the supply on R3 was 5V, driving the output HIGH would still result in current flow into the MCU. Would sinking current (through M1) when the output is driven HIGH be a problem? My understanding is that typically, when it is desirable to sink current, the output should be driven low (for current to flow to GND through M2).
Does this present a fundamental problem with how CMOS digital outputs are meant to be used? Can current be "sunk" to VCC? Would this cause problems with the intrinsic body diode of the P-Channel M1 always conducting some current, and is that an issue?