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We have a arm SoC(system on chip) connected with I2S to a DSP (digital signal processor). SoC and DSP both support 48khz, 8 channel and 16bits in TDM mode.

Is it possible to use this interface to send 24channel, 16khz and 16bits as DSP is able to encode the data and SoC can decode this encoded data?

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It has the bandwidth do do so, but you may have to modify the protocol or add hardware to distinguish the channels. You say that your SoC and DSP can support 8 channels, so that implies that there's some mechanism in addition to I2S, which typically supports only two channels with the frame sync distinguishing between the two. If it's specified at up to 8 channels, then that might be a designed-in limitation, or if it's specified for 8 channels at 48KHz, it may be extensible to 24 at the lowest rate.

Perhaps the simplest solution if only 8 are supported natively is to use 2 GPIOs to extend the native 8-channel addressing scheme.

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  • \$\begingroup\$ Both SoC and DSP supports TDM and if both agrees on a fixed packet format than I think this is doable. We don't need to distinguish between the channels at the protocol level but once the data is recorded and as we agreed on the fixed format, SoC side will know that recorded X data will have Y channels. However, some kind of sync also needs to be added in case the DSP starts before SoC to resync at the SoC side as Left and Right toggling wouldn't tell you the start of the first channel information. \$\endgroup\$ – user3053970 Jul 27 '18 at 17:23

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