I have a hardware structure (described in logic diagram consisting of adders and multipliers) that is extremely regular, i.e., one small hardware is repeated again and again in the structure with regular pattern of interconnects. for example, see the schematic below.
The hardware on the right is formed using multiple copies of the small hardware element on the left. Now, suppose I have another structure that has the same number of Z-elements (in the above example image) but it doesn't follow any regular pattern of interconnects between different layers, i.e., the interconnections between Layer 1 and 2 are random. My question is which of these hardware will be better (in terms of power efficiency, area or any other respect) or they will both be identical in terms of performance (power, area etc.) ? Please answer both with an FPGA- and ASIC-based implementation platform in mind. Any references are appreciated.