I have an input device that can write in either serial, 8-bit parallel, or 16-bit parallel. I know the input frequency and max write speed of those data formats.
I am given a requirement of a "64 Byte" FIFO, with a word consisting of 4 Bytes. I want to test this generic VHDL code I found online. The constants required to modify are "DATA_WIDTH" and "ADDR_WIDTH". I can see from the code, 1 word is associated with ADDR_WIDTH.
... constant FIFO_DEPTH : integer := 2**ADDR_WIDTH; --given equation??? signal pNextWordToRead : std_logic_vector(ADDR_WIDTH - 1 downto 0); ...
But it also calculates the depth for you. So if I first plug in my word size, I can calculate my depth. Could I also calculate my Data Width as
DATA_WIDTH = 64 byte / word size (derived from FIFO size = width x depth)? If I am using the wrong values, how would I calculate my depth properly?
So is the Data width not the same as the FIFO width? If the data width is less than the address width, then it would take more than 1 cycle to write a full address.
This implementation makes sense to me at the moment because my depth is a lot and I properly will not overflow (my read clock is a lot faster too).