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I have an input device that can write in either serial, 8-bit parallel, or 16-bit parallel. I know the input frequency and max write speed of those data formats.

I am given a requirement of a "64 Byte" FIFO, with a word consisting of 4 Bytes. I want to test this generic VHDL code I found online. The constants required to modify are "DATA_WIDTH" and "ADDR_WIDTH". I can see from the code, 1 word is associated with ADDR_WIDTH.

snippet:

...
constant FIFO_DEPTH : integer := 2**ADDR_WIDTH; --given equation???
signal pNextWordToRead : std_logic_vector(ADDR_WIDTH - 1 downto 0);
...

But it also calculates the depth for you. So if I first plug in my word size, I can calculate my depth. Could I also calculate my Data Width as DATA_WIDTH = 64 byte / word size (derived from FIFO size = width x depth)? If I am using the wrong values, how would I calculate my depth properly?

So is the Data width not the same as the FIFO width? If the data width is less than the address width, then it would take more than 1 cycle to write a full address.

This implementation makes sense to me at the moment because my depth is a lot and I properly will not overflow (my read clock is a lot faster too).

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  • \$\begingroup\$ So your writing 16 words of 4 bytes each for a total of 64 bytes. Try not to get lost in the simplicity of it. \$\endgroup\$ – Sparky256 Jul 29 '18 at 0:31
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    \$\begingroup\$ You asked this question two days ago in SE: "stackoverflow.com/questions/51550077/…" where you got one down vote. 1/ "I am given a requirement" suggests this is a school assignment. 2/ If you are not sure about your specifications, you go back to whoever gave you the assignment and ask for clarification. You do not guess, you do not ask somebody else! \$\endgroup\$ – Oldfart Jul 29 '18 at 6:26
  • \$\begingroup\$ I don't understand the simplicity of 16 words of 4 bytes translating to the bit depth or bit width that is required for VHDL though. I'm sorry it's simple but I know the max is 16 bits in parallel. 4 bytes is 32 bits. \$\endgroup\$ – Cit5 Jul 30 '18 at 2:31
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    \$\begingroup\$ I'm sorry I didn't know I had to specify I previous asked this question. Yes I asked in stack overflow but it was taken down and downvoted because it was not a programming question (in the comments). I don't think this is homework question but I'll ask the person first thing on Monday, I was trying to solve something that is suppose to be simple on my own. I don't think double checking online sources is considered guessing. Again, I asked is it possible to calculate width and depth based on this simple specification. \$\endgroup\$ – Cit5 Jul 30 '18 at 2:35
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I think your confusion comes from the fact that the code you posted is referring to an "address", while normally when you utilize a FIFO, there is no concept of an "address". As a normal user, you just "push" data onto the FIFO and "pop" data off of the FIFO. This makes the application of a FIFO easy to comprehend. You still need to understand and consider the concept of the FIFO's data width, and the FIFO's depth.

If you are designing a FIFO, then you need to realize that a FIFO is just a RAM block with some logic that controls the read/write address automatically (and internally). Since RAM blocks do have address lines, we at least need to consider them. This is easy: The depth will be 2^(numAddrBits). Or alternatively, the number of Address bits must be, at minimum, ceil(log2(depth)).

This picture may help you visualize:

enter image description here

The fundamental task of designing a FIFO is to determine how many bits you really need to store. In your example, this was 64 bytes, or 512 bits. The next thing you should do is decide how you want these bits organized. For example, You could choose for your FIFO to have 8-bit word length, and a 64 word depth, meaning your RAM would need ceil(log2(64)) = 6 address bits.

For your example, the determination was already made: Word length = 4 bytes.

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