I want to count number of "clock enable" signal inside flip flop.
I learn from tutorials that the output value should be assigned for all combinations of input.
However I don't know how to add counter that counter should be updated only if clk_enable = 1.
module count_ce ( input logic reset_n, input logic clk, input logic clk_enable, output logic[63:0] counter ); always_ff @(posedge clk or negedge reset_n) begin if (!reset_n) begin counter <= 64'd0; end else begin if (clk_enable) begin counter <= counter + 1; end else begin //counter <= counter; // ? counter <= 64'd0; // have to assign counter for else-case otherwise infer latch? end end end endmodule