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I'm currently re-designing a 12-layer pcb. The only thing I am still struggling with is the routing of the ethernet.

The layer stackup is as follows:

  1. Top Layer
  2. GND_1
  3. MidLayer_1
  4. PWR_1
  5. MidLayer_2
  6. GND_2
  7. PWR_2
  8. Midlayer_3
  9. GND_3
  10. Midlayer_4
  11. PWR_3
  12. Bottom Layer

I have read a lot of ethernet design guidelines which mostly stated that preferably the RJ45, Ethernet magnetics and Tx and Rx lines should have a ground keepout beneath them. Now here is my confusion I just read this paper: Ethernet Ground and it states

When designing 4 layer boards, the ground plane should exist on layer 4, assuming the differential pair is routed on layer 1. On 2 layer boards, the ground plane can be located on layer 2, the adjacent layer to the TX and RX signal pairs. Under no circumstances should a ground plane exist under the magnetics, the RJ45 connector or in between the magnetics and RJ45 connector.

I find the part of "when designing 4 layer boards, the ground plane should exist on layer 4 (layers further away?)" and the "under no circumstances should a ground plane exist under the magnetics, the RJ45" very conflicting and would love some clarification.

TLDR Questions:

When following the rule of having a ground keepout around the ethernet, does this keepout have to be on all 12 layers. Or only the nearest adjacing layers?

PS: there are some related ethernet questions about layout, Stackexchange question but it doesn't completely satisfy the "why" part I am interested in and does not address the multilayer design.

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  • \$\begingroup\$ you don't want a ground plane under the ethernet transformers, ethernet is suposed to be isolated. \$\endgroup\$ – Jasen Jul 30 '18 at 8:37
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The answer is: it doesn't matter how you route the lines if the impedance is kept to 100Ω.
The requirements provided in the document might be good for one form of 100Ω microstrip line, but there is more than one way to make a differential pair with an impedance of 100Ω including ways to do this between planes.

There is a great write up here of how to do this:
How do I lay out PCB traces for a given "differential impedance"

When following the rule of having a ground keepout around the ethernet, does this keepout have to be on all 12 layers. Or only the nearest adjacing layers?

Depends on the impedance of the lines, what they were going for in the article I'll never know. Placing the ground layer on one of the outside layers in a 4 layer board limits your options for routing impedance controlled signals in my opinion, and forces you to use an inside layer(layer 3) for signal traces that need a ground next to them. I'd rather put the signal lines on layer 1, ground on layer 2, power/signal/ground layer 3, power/signal layer 4.

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Ethernet signals should be routed so that they have 100 ohm differential impedance. This can be achieved by using different stackups, but usually the layer with the differential traces will be adjacent to a ground plane layer to achieve the desired impedance. As far as the transformer goes, it depends on whether it is a discrete transformer, or integrated into an RJ45 jack. With discrete transformers it is recommended to separate the ground planes between each side of the transformer to prevent a path for noise coupling. It is also common to bridge the gap between grounds with several capacitors in case they are needed. It is not necessary or desired to have separate grounds when using an RJ45 jack with integrated magnetics which simplifies the design.

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  • \$\begingroup\$ So you're saying that ground keepouts or not don't really matter as long as you achieve the desired layer stackup to reach the 100ohm impedance? Do you have any references for this, I can read into? \$\endgroup\$ – Remco Vink Jul 31 '18 at 6:06
  • \$\begingroup\$ Ground keepouts do matter when using a discrete transformer. See the following Intel layout guidelines: intel.com/content/dam/www/public/us/en/documents/design-guides/… \$\endgroup\$ – EE_socal Aug 1 '18 at 16:37

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