How an electrolytic capacitor survives in negative half cycle?

An electrolytic capacitor doesn't like higher voltage at its opposite terminal i.e higher voltage should only be at positive terminal as per convention.If that so how the capacitor survives in this circuit as AC signal travels in either direction.The capacitor should die in negative cycle.Why it is not happening?

simulate this circuit – Schematic created using CircuitLab

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• I don't see were it is going to get negative voltage. The circuit is DC-coupled. Commented Jul 30, 2018 at 16:15
• If I get output as an ac signal then tell me your analysis? Commented Jul 30, 2018 at 16:19
• The voltage across C2 can't ever go negative; R2 ties the two terminals together, and Q1 can only ever supply voltage above ground. Commented Jul 30, 2018 at 16:19
• Alternating current but DC voltage Commented Jul 30, 2018 at 20:33

If you do a small signal analysis the capacitor sees a small negative voltage, however that is actually on top of the bias which is a relatively large positive voltage (5V or something like that). The voltage across C2 can never be negative for a passive load.

Presumably you would add a collector load resistor in order to see some output, because there will be none at the collector and precious little at the emitter.

Note: That's assuming "normal" conditions. If you feed a 10kV 1kHz sine wave into the circuit you will see negative voltage across the 100uF cap, but other bad things will likely be happening too

Current can flow into and out of an electrolytic capacitor and thus that can be regarded as an alternating current but, that does not mean the capacitor suffers a reverse voltage across its terminals.

I assume you are calling the stub wire connected to the collector of Q1 the output.

1. Your output is tied directly to the 12 V source, so the output is a constant 12 V with no AC component.

2. If you fix the circuit to allow for an AC output, you will get an AC output biased around +6 V (if you design it optimally). The instantaneous output voltage will never be negative.

3. The emitter of Q1 will only ever source current (barring some undesired capacitive ringing effects), so C2 will always have a positive voltage.