# Adding to a sum variable produces a “reals can't be synthesized” error in verilog

First, a disclaimer that this is my first time using verilog and I don't really know anything. My code is as follows:

module trapverilog(
input CLK,
input SIGNAL,
input x,
output reg OUT
);

reg[1:0] yreg;
real sum = 0;

always @(posedge CLK)
begin
yreg = SIGNAL; //should shift automatically
sum = ((yreg[0] + yreg[1])*x/2) + sum; //treats x as plain h, change if treated as h/2
OUT = sum;
end

endmodule


It produces an error saying that real data types can't be synthesized referring to the sum = ((yreg[0]... line. What does this mean, and how can I fix it?

The intent here is to create an FPGA that can perform the trapezoidal integration method which is just $$A = \frac{(b-a)(y_1+y_2)}{2}$$ In my program I'm taking $$\frac{b-a}{2}$$ as an input x and I'm also talking in a clock signal CLK and a signal to be integrated, SIGNAL.

I create a two spot register, yreg, with and when CLK is high I set yreg = SIGNAL intending to shift the old value into the next slot - that is, I end up with y1 shifting to y2 and the new value goes into y1. Then I calculate the area following the formula given above and add it to sum and set the output, OUT equal to sum. The problem in this case being that sum can't be added to.

There are probably other errors that I don't know about so I apologize for those in advance. Any help would be appreciated.

• HDLs might contain constructs which cannot be translated into a hardware and only good for simulations. Apparently the real type is one of these. – Eugene Sh. Jul 31 '18 at 16:36
• You have other problems too. There is not automatic shift. You have to make it explicit. And you should use the non blocking assignment (<=) for assignments inside always @posedge. – Matt Jul 31 '18 at 23:53
• And then you'll probably see the latency bigger than you need because you have extra pipeline stages that you don't want (assign to sum as a flip flop and then out is another one). Put non flip flop assignments outside that always block (use an assign or a combinational always block). – Matt Jul 31 '18 at 23:56
• You will probably learn a lot if you read the Xilinx Synthesis Guide. – The Photon Aug 1 '18 at 2:11