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I've read about loops that a PCB designer should avoid them "mostly about ground loops" but i think I've read also about power.

so in this case, is this wrong: ??? enter image description here

enter image description here

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    \$\begingroup\$ You want to keep the ground return paths as close as possible to the voltage supply path as it is one big current loop. The larger the loop area the more more EMI radiation and susceptibility \$\endgroup\$ Aug 2, 2018 at 14:10
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    \$\begingroup\$ While there are some small loops here, multiple vias has a positive effect by reducing the inductance and resistance between the buried plane and the balls/pads you're trying to deliver power to. I'd keep the multiple vias. \$\endgroup\$
    – The Photon
    Aug 2, 2018 at 17:16
  • \$\begingroup\$ I not sure I would call them loops. They are really parallel paths (vias) providing current from a power net to a destination. While there are always exceptions, generally more vias are better because they serve to reduce the path resistance and inductance. \$\endgroup\$
    – SteveSh
    Apr 22, 2021 at 18:23

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Trace loops are an excellent way to introduce noise to your lines. Either it is from a ground or a "positive" trace, magnetic flux that passes through the loop will induct a voltage to the resistance of the copper trace, which eventually will add up to your "normal voltage". Such magnetic fluxes can be due to power grid (50 or 60 Hz), low-end SMPS, rf signals, etc.

An excellent source for information about pcb design is analog's Linear Circuit Design Handbook (which is free to download) and from which is the following Figure

Chapter 12, Figure 12.19: Nonideal and Improved Signal Trace Routing

The traces you have pointed out are indeed loops. I hardly believe that they will create any notable noise, since they are small, but it is always a good practice to avoid them.

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  • \$\begingroup\$ this is good, now the photos in the question are coming from internal regulator to VDDCORE of arm core . is there any benefit of doing these small loops? this board is designed by atmel so i guess they shouldnt have this "bad practice" and thats where my question came from .. the right big capacitor is the decoupling for vout of regulator \$\endgroup\$ Aug 2, 2018 at 16:59
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    \$\begingroup\$ I really can't think of any good coming from these loops. Maybe the multiple adjacent vias act as a metal shield that does not permit magnet flux to pass through the loop, so it doesn't matter. Decoupling caps (electrolytic in parallel with MKT/MKP for voltage regulators and MKT/MKP for other ICs) always help to stabilize Vcc. The closer they are to Vcc and GND pins, the better. \$\endgroup\$
    – thece
    Aug 2, 2018 at 19:51
  • \$\begingroup\$ Nothing wrong with this answer, but I really don't think it addresses what the OP as asking about - small loops created by parallel paths (multiple vias) in the power net. \$\endgroup\$
    – SteveSh
    Apr 22, 2021 at 18:26
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Consider just a sensor feeding a voltage to an ADC Analog Digital Converter. The ADC takes charges from the sensor, and performs the digitization. Those charges --- electrons ---- may remain inside the ADC for binary-search conversion from charges into digital-decisions, but identical charges must be returned to the Sensor.

That return-path is called Ground. Any voltage in the Ground-path causes a measurement error.

The resistance of a square of copper foil ---- if the standard thickness of 1.4 mils or 35 microns --- is 0.000500 ohms (500 microOhms) measured across opposite edges. For any size square.

Draw out the return path of your signal charges, and also determine what OTHER charges will share that return path. Why? because charges explore ALL POSSIBLE return paths, proportional to conductance.

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It may be complaining because of the layer transitions. Layer transitions can be nasty for higher speed signals and analog as well. If you can, especially if they're sensitive signals, try to route them on the same layer coupled with a ground. Your board looks like its' already very tight so there may not much you can do in that department.

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  • \$\begingroup\$ there is capacitors in the bottom layer ... they just routed the 2 balls in top layer ... they allready placing vias to capacitors \$\endgroup\$ Aug 2, 2018 at 17:05

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