# Does Sallen-Key filter need a high impedance load?

I am using the circuit below to monitor the output of a piezoelectric diaphragm, represented by a sine wave generator and capacitor C3.

The circuit is powered from a split supply (+5V/-5V) derived from a linear power supply (230V, 50Hz). I need the full rail-to-rail dynamic range (or as close as possible).

The functions of the amplifiers are as follows:

• U1 - charge amplifier, frequency range of interest: 1Hz-60Hz

• U2 - Sallen Key filter, low pass, fc = 110Hz

• U3 - scale and bias amplifier to convert U2 output to 0V min, +3V max, suitable for ADC.

The circuit works in simulation, but in practice I find that a high amplitude mechanical impulse on the piezoelectric disk causes U3 to oscillate'. (U3 seems to output the input plus narrow pulses which jump to the +5V rail at a frequency of 50Hz). The oscillation will eventually disappear (after about 30-40 seconds) if the piezo is left untouched. I checked the power supply rails - they are clean with little ripple, even when the oscillation is happening.

If I disconnect U3 and monitor the output of U2 only, the problem is not present. I found that I could "cure" the oscillation in the circuit by putting a voltage follower amplifier between U2 and U3 and then reconnecting U3. I'd prefer not to use a voltage follower op amp as it introduces additional noise.

My question is: Does U3 cause a problem for the stability of U2 at high frequencies? The impedance of C101 will be low for a high frequency impulse on the piezo disk and U2 is trying to drive current to support this as well as maintaining the correct current through R5 to keep the input voltages on pin 2 at around 1V d.c.

Perhaps there's a better way to offset the output signal?

• I'd be worried about the output from the LMC6041. Have you looked at it? – Andy aka Aug 2 '18 at 14:46
• Hi Andy. Thanks for your comment. The output from U1 seems stable. Please may I ask what worries you about it? My understanding is that U1 follows a common charge amplifier design approach, similar to figure 3 in ti.com/lit/an/sloa033a/sloa033a.pdf Would welcome your further thoughts on this. – DB17 Aug 2 '18 at 15:29
• What does your layout look like? How much capacitance do you have for power filter caps on each op amp? Do you have any large sources of parasitic inductance? – Voltage Spike Aug 2 '18 at 15:44
• OK, you needed to prove it wasn't an upstream signal problem. Maybe a scope shot will help . – Andy aka Aug 2 '18 at 16:09
• Things you might try: These devices have poor power supply rejection at high frequencies so you will need to be especially careful with your power supply and ground lines near each of the amplifiers. Especially you need ceramic capacitors between both power rails of U2 and C102-GND, and make sure the current path from the power supplies to U2 are separate from the other amplifiers. You could also add a high-R bleed resistor in parallel with the piezo rather than leaving it floating. Finally, you might add a small passive RC before the filter to knock out the really high frequencies. – John Birckhead Aug 2 '18 at 18:42