I am trying to build an abc to positive/negative/zero components transformation block (in LTspice), I did it, but sometimes I get erroneous behaviour: DC levels seem to be "omitted" at the output for an abc > 120 > abc chain.

The schematic I'm using is this:


and the waveforms are these:


You can see that all waveforms are identical, but b/b* and c/c* have a DC difference between them. Here are the differences:


(in1, in2 and in3 are the a, b and c in the previous screenshots)

The signals are these:

  • all three phases have unity fundamental + 3rd/3, 5th/5 and 7th/7 all positive harmonics;
  • phase a has twice the amplitude;
  • phase b has 0.1Vdc;
  • phase c has 0.3rad phase lead.

Is this normal? Are DC bias levels "left behind"?

In order to build the schematic for a practical use, I had to maneuver a bit through the equations to avoid the \$\pm \frac{2 \pi}{3} \$ delay, and so I transformed \$e^{\pm j \cdot \frac {2 \pi}{3}} = -\frac{1}{2} \pm j \frac{\sqrt{3}}{2}\$, which left only \$j\$ to take care of, a minor leap for SPICE-kind.

  • \$\begingroup\$ I did say "Hello everyone", but it got deleted. When I tried to edit, the previous added images that I can't upload (<10 points) reappeared, so I am adding the greetings at the end, apologies for that. (edit3) I just saw that "Thank you in advance, Vlad" is no more, either. It's my first time here so I don''t know what happened. \$\endgroup\$
    – Vlad
    Aug 27, 2012 at 14:07
  • 2
    \$\begingroup\$ Sometimes moderators edit content for improving a question or answer in terms of its clarity, conciseness, aesthetics, rule-obedience, etc. Most times, they have good or necessary taste with edits, so don't worry :-) \$\endgroup\$
    – boardbite
    Aug 27, 2012 at 14:32
  • \$\begingroup\$ I have found the problem, it was an error from my calculations: after changing from +j to -j, I forgot to change the sign. My mistake. \$\endgroup\$
    – Vlad
    Aug 28, 2012 at 6:15
  • \$\begingroup\$ I am sorry, I jumped to conclusion. When both b and c phases have (the same) DC, then all's well, it seemed the culprit was caught, but it wasn't. The result is still the same: any DC at phase b results in b* with zero bias and c* with b's DC value, and vice-versa. Phase a is unaffected. I don't understand, any help is much appreciated. \$\endgroup\$
    – Vlad
    Aug 28, 2012 at 7:14
  • \$\begingroup\$ I just moved the edit to the new "location", it will do. \$\endgroup\$
    – Vlad
    Oct 2, 2012 at 7:12

1 Answer 1


In the meantime, the solution was found: the culprits are the delay lines.

The approach I tried was to have instantaneous values rather than magnitude/angle. For this, I tried to mathematically derive the circuit in order to use only a \$-90^\circ \$ delay instead of the \$\pm 120^\circ \$ ("a"), but here is the catch: symmetrical components are meant to be a phasor analysis, and using the delay line as \$-j\$ , for a \$0.1_{DC}+1\angle 0 \$ input (DC separate for better view) I would get \$-j0.9\$ , which explains the erratic behaviour for different DC unbalance levels.

Lesson learned, hopefully remembered when needed. :)


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