I am still a beginner and I keep getting this error, can anyone help pls?

library IEEE;

use IEEE.STD_LOGIC_1164.all;


entity ClkDivider is

port ( clk_in : in STD_LOGIC;
        reset : in STD_LOGIC;
     clk_out : out STD_LOGIC);

end ClkDivider;

architecture behaviour of ClkDivider is

signal counter: integer := 0;

signal temporal: integer range 0 to 499 := 0;

    clock_divider: process (reset, clk_in) 


if (reset = '1') then

            temporal <= 0;
            counter <= 0;

        elsif rising_edge(clk_in) then
            if (counter = 499) then
                temporal <= not (temporal);
                counter <= 0;
                counter <= counter + 1;
            end if;
        end if;
    end process;

    clk_out <= temporal;
end behaviour;
  • \$\begingroup\$ I understand, that it is not allowing you to post code only question. It's for a reason. Please format properly. \$\endgroup\$ – Eugene Sh. Aug 3 '18 at 19:56
  • 4
    \$\begingroup\$ I rarely use VHDL but to me the error message says that the not operator is not defined for integers. \$\endgroup\$ – Oldfart Aug 3 '18 at 20:21

The NOT operator is not defined for integers, you can only use it on formats like std_logic, std_logic_vector, signed, unsigned, bit, bit_vector, ...

Why ? Because VHDL don't assume any hardware implementation for integers : It can be binary numbers, but it is not mandatory. The synthesiser is free to use any encoding. For example, your simple counter could be implemented with a linear feedback shift register and it would be smaller and faster (in an ASIC) than a binary adder.

Conversion functions are available in the IEEE.numeric_std.ALL library for integer <-> signed/unsigned conversions.

Anyway, there are a few other problems with your code.

  • The counter integer has no range, which is bad coding, particularly for synthesisable code.
  • cly_out is a std_logic, temporal is an integer, what do you intent to do with clk_out <= temporal ?
  • \$\begingroup\$ LFSRs are faster in FPGAs too due to the carry chain. \$\endgroup\$ – user110971 Aug 4 '18 at 1:00

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