# Error (10327): VHDL error at clkdivider.vhd(27): can't determine definition of operator “”not“” — found 0 possible definitions

I am still a beginner and I keep getting this error, can anyone help pls?

library IEEE;

use IEEE.STD_LOGIC_1164.all;

use IEEE.NUMERIC_STD.ALL;

entity ClkDivider is

port ( clk_in : in STD_LOGIC;
reset : in STD_LOGIC;
clk_out : out STD_LOGIC);

end ClkDivider;

architecture behaviour of ClkDivider is

signal counter: integer := 0;

signal temporal: integer range 0 to 499 := 0;

begin
clock_divider: process (reset, clk_in)

begin

if (reset = '1') then

temporal <= 0;
counter <= 0;

elsif rising_edge(clk_in) then
if (counter = 499) then
temporal <= not (temporal);
counter <= 0;
else
counter <= counter + 1;
end if;
end if;
end process;

clk_out <= temporal;
end behaviour;

• I understand, that it is not allowing you to post code only question. It's for a reason. Please format properly. – Eugene Sh. Aug 3 '18 at 19:56
• I rarely use VHDL but to me the error message says that the not operator is not defined for integers. – Oldfart Aug 3 '18 at 20:21

The NOT operator is not defined for integers, you can only use it on formats like std_logic, std_logic_vector, signed, unsigned, bit, bit_vector, ...
Conversion functions are available in the IEEE.numeric_std.ALL library for integer <-> signed/unsigned conversions.
• cly_out is a std_logic, temporal is an integer, what do you intent to do with clk_out <= temporal ?