# Basic definition of duty cycle

Does the definition of duty cycle indicate only the percentage of time that the level is asserted? For example, if a 10 Hz square wave is de-asserted for 5 of those 10Hz cycles and asserted for 5 of the 10Hz cycles, would that represent a 50% duty cycle? If I represent each of the de-asserted 10 Hz cycles in a single second as a 0 and each of the asserted 10 Hz cycles in that same second as a 1, I could represent a 50% duty cycle as 0000011111. But if it is only the percentage that matters, I could also get 50% by the sequence 0101010101. In the definition of duty cycle, is it necessarily the case that the asserted periods be consecutive and that the de-asserted periods also be consecutive?

• duty cycle percentage is measured within a single cycle of the signal ..... high for 5 seconds and low for 5 seconds equals 50% duty cycle ..... high for 1 second and low for 9 seconds equals 10% duty cycle Aug 5, 2018 at 1:24
• I am tempted to write a one word answer: "Yes." It probably wouldn't be well received, but it would technically answer your question perfectly. en.wikipedia.org/wiki/Duty_cycle - For example 1010 would be a duty cycle of 50%, as would a repeating signal of 1111 1011 1111 1111 0000 0000 0000 0010 (and countless other permutations). Aug 5, 2018 at 1:35
• When discussing duty cycle, there is generally an assumption that the frequency is fixed. So the percent is always calculated over a single period. If the output is de-asserted for an entire period, you might refer to that as a skipped pulse. Some regulators will go into a skip-pulse mode under certain conditions. Aug 5, 2018 at 3:09