I'm trying to make a linear regulator using an op amp and a pass transistor.

Here is the circuit:


From my limited understanding you can predict the stability of the circuit's feedback loop by looking at the loop gain. By plotting V(fb)/V(in) I'm told the circuit has a phase margin of ~75 degrees and a gain margin of ~25dB.

When tested on a breadboard however the output is oscillating at around 7kHz at 100mV pp. I can reduce the frequency of this oscillation by increasing R5. I can also reduce the amplitude down to nothing by increasing C2 to 68nF (though I would like to avoid this to keep the response time down). The question is, What is causing the discrepancy between LT spice and reality?

Bode plot:

Bode plot:

Scope trace:

Scope trace:

  • \$\begingroup\$ Upload the images to imgur and provide links. Someone will edit them into your question. You don't have enough rep to do it yourself, at the moment. \$\endgroup\$ Aug 7, 2018 at 13:19
  • \$\begingroup\$ What real load did you use? What length power leads? What input supply voltage? Did you consider that a real input supply needs real decoupling capacitors? Have you ever seen a practical voltage regulator chip not having an input capacitor? \$\endgroup\$
    – Andy aka
    Aug 7, 2018 at 13:31
  • \$\begingroup\$ Does that circuit have some dead zone in the output control? If so then phase margin doesn't make a lot of sense for analysis. Try simulating the transient response to a step in output load and a step in input voltage. \$\endgroup\$ Aug 7, 2018 at 13:33
  • \$\begingroup\$ I would start by building the circuit on a proper board, instead of a breadboard, because the parasitic of that board will push your loop response all over the place. \$\endgroup\$
    – Joren Vaes
    Aug 7, 2018 at 13:33
  • \$\begingroup\$ @SpehroPefhany I've added the plot and scope trace now. What do you mean by dead zone? I simulated a sweep of the input and plotted the output and it seems to be completely linear but I'm not sure if that's what you're referring to. Edit: I've done a fair few step response simulations and there don't seem to be any kinks in the rising/falling edges \$\endgroup\$
    – astnstn
    Aug 7, 2018 at 13:33

1 Answer 1


The problem is you have not modeled your system accurately. Simulating circuits works as long as the physical system is modeled correctly.

The question is, What is causing the discrepancy between LT spice and reality?

The answer is probably parasitics, wires breadboards and solder all have parasitic resistance and inductance. There is also parasitic capacitance between any two points of metal. The problem with SPICE is the nodes are all superconducting, there is no inductance or resistance between nodes.

If you built this on a breadboard, the grounding system may be insufficient. The ground plane on a PCB gives a small amount of capacitance to all traces, and also decreases inductance.

An 8" jumper wire has roughly 0.140mΩ of resistance and 0.180uH of inductance (measured with LCR meter)

A breadboard has roughly 2-4pF of capacitance between two rows. With four inch wire leads the capacitance jumps to 10's of pF's

Wires can also add inductance to a circuit, you can estimate the inductance with a calculator Breadboards are not great for prototyping. If you add in the main sources of inductance the model should match the physical world. Sometimes it can be a bad model also, if this is suspected, you can test the model in spice and compare the results with the datasheet to find discrepancies


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