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I'm designing a plugin card that's powered at 12V from the main board. Now, I need a 3V3 and a 2V5 voltages on the card, so I'm using two buck converters MUN12AD03-SH (I'm supposed to use this specific converter, so I can't change that).

The signal for enabling the converters comes from the main board and is active-low (I can't change that as well), while this the converter's enable is active-high, therefore I'll have to use an inverter gate.

So the question is what's the wisest way to power this inverter gate if the DC-DC converters aren't enabled yet (only have 12V)? I wasn't able to find a 12V tolerant inverter gate. Can I use a voltage divider as the inverter gate won't draw big currents? Or should I use another buck or LDO or something else?

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    \$\begingroup\$ some small MOSFETS like 2N7002 instead of an inverter gate. \$\endgroup\$ – EE_socal Aug 7 '18 at 16:47
  • \$\begingroup\$ This is second time in two days I see someone attempting to use LDO for signal level conversion. Amazing. \$\endgroup\$ – Maple Aug 7 '18 at 17:01
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    \$\begingroup\$ Search for "Level Shifters" \$\endgroup\$ – Sunnyskyguy EE75 Aug 7 '18 at 17:05
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    \$\begingroup\$ This is typical XY problem. "How to power inverter gate" only comes into play because the gate is chosen as a solution Y. The actual problem X is extremely simple: "given 12V power supply how to send anything from 1.5V to 12V to EN pin when control signal is Low". And the answer is - just use a single transistor or mosfet, as @EE_socal suggested in very first comment \$\endgroup\$ – Maple Aug 7 '18 at 17:14
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    \$\begingroup\$ You can use LDO to power logic gate. You can use another DC-DC converter or PoE or maybe hydrogen fuel cell to power a single gate. All I am saying is that complex solution does not make any sense for such a trivial problem, even if it works. \$\endgroup\$ – Maple Aug 7 '18 at 22:53
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By the way, this is the buck converter you listed, its enable pin supports voltages up the \$V_{IN}\$ value.

I don't know if this is the 'wisest' way, as you call it, but you could do something like this:

schematic

simulate this circuit – Schematic created using CircuitLab

I am assuming the enabling signal would be high when not asserting and low when asserting. If it is open drain, you could pull up the MOSFET's gate anyway—that is why I added the optional pullup.

So in summary, when the enable signal coming from the main board is low (0V), the MOSFET is OFF and the EN pin on the buck converter side will be pulled high (converter is ON). When the enable signal coming from the main board is high (12V) or open drain, the MOSFET's gate will be high and the MOSFET is ON—this will force a low voltage at the EN pin on the buck converter side, thus disables it (converter is OFF).

You could do a similar thing for the other buck converter. Hope this helps.

Reference: MUN12AD03-SH

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  • \$\begingroup\$ I simulated the circuit but the problem is the enabling signal doesn't get low enough. According to the datasheet the falling threshold voltage is 0.4V. I could use a bigger Rp but the thing is that the enabling signal is 3.3V so it'd have to be ~500k. Is that okay? \$\endgroup\$ – Luka Aug 8 '18 at 9:31
  • \$\begingroup\$ Okay, apparently there was a problem with the spice NMOS model. I now chose a specific NMOS and the voltage is as it should be. Just ignore the previous comment. \$\endgroup\$ – Luka Aug 8 '18 at 11:11
  • \$\begingroup\$ @Luka Glad it helped. I can see where you had the issue initially—the generic NMOS model in LTSpice probably needs even higher voltages at the gate to turn it on. \$\endgroup\$ – Big6 Aug 8 '18 at 17:23
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First, please note that some CMOS gates are 12V tolerant, like the old-fashioned 40xx series (CD4069); this will work without overhead if your circuit doesn't need fast time response.

Then, assuming your gate draws little current, as it is often the case, you can indeed use a voltage divider, but make sure it is not too much loaded by the chip (\$ R_{load} >> R_1 || R_2 \$ as a rule of thumb).

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