I'm routing a large BGA SRAM that is connected to a BGA FPGA, and there's about 40 signals altogether connecting the two. I'm using Henry Ott's recommended 8-layer stackup:
1 ________________Mounting Pads/Low Freq. Signals
4 ________________High Freq. Signals (SRAM Layer 1)
5 ________________High Freq. Signals (SRAM Layer 2)
8 ________________Low Freq. Signals/Test Pads
I've fanned out the BGA such that all the SRAM pins are on layers 4 and 5. However, my routing results in a lot of parallel traces on adjacent layers, and I'm concerned about crosstalk: (I'm in the process of length tuning. SRAM traces are different shades of blue, indicating address/data/control groups, not layers. Sorry for any confusion.)
Questions I have about SRAM routing:
Should I revise my stackup to seperate these layers with a ground, or should I just try to avoid traces that are directly adjacent for long distances? Should I try to get all signals onto one layer using vias, or is that even worse?
On a related note, when I'm calculating trace-impedence of signals on layers 4/5, is that calculated as a microstrip or an asymmetrical stripline? It's not open to the air, but it's also not sandwiched directly between two ground planes.
Finally, this is unrelated, but for asynchronous SRAM do I need to length-match all signals or are there groups like in DRAM? I'm under the impression that for a write, for example, address and input data would need to arrive together, hence everything is length-matched.
This is my first high-speed design like this, and any advice would be greatly appreciated.
EDIT: SRAM part number for reference is CY62187EV30LL-55BAXI