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When I set up my module, I have code like

input signed [7:0] SIGNAL

but in the UCF I want to assign each bit individually. Currently my code in the UCF looks something like

NET "SIGNAL[0]" LOC = P35 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST;

(With the number in brackets replaced up to 7, obviously.) But this doesn't seem to be working. I am using a Mimas Spartan 6 FPGA.

How can I properly assign each individual bit of the register in the UCF for this board?


Full UCF code:

NET "CLK" LOC = P126;
NET "SIGNAL[0]" LOC = P35 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST;
NET "SIGNAL[1]" LOC = P34 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST;
NET "SIGNAL[2]" LOC = P33 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST;
NET "SIGNAL[3]" LOC = P32 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST;
NET "SIGNAL[4]" LOC = P30 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST;
NET "SIGNAL[5]" LOC = P29 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST;
NET "SIGNAL[6]" LOC = P27 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST;
NET "SIGNAL[7]" LOC = P26 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST;
NET "x[0]" LOC = P24 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST;
NET "x[1]" LOC = P23 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST;
NET "x[2]" LOC = P22 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST;
NET "x[3]" LOC = P21 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST;
NET "x[4]" LOC = P17 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST;
NET "x[5]" LOC = P16 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST;
NET "x[6]" LOC = P15 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST;
NET "x[7]" LOC = P14 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST;
NET "SUM[0]" LOC = P12 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST;
NET "SUM[1]" LOC = P11 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST;
NET "SUM[2]" LOC = P10 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
NET "SUM[3]" LOC = P9 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
NET "SUM[4]" LOC = P8 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
NET "SUM[5]" LOC = P7 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
NET "SUM[6]" LOC = P6 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
NET "SUM[7]" LOC = P5 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
NET "SUM[8]" LOC = P2 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
NET "SUM[9]" LOC = P1 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
NET "SUM[10]" LOC = P142 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
NET "SUM[11]" LOC = P141 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
NET "SUM[12]" LOC = P140 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
NET "SUM[13]" LOC = P139 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
NET "SUM[14]" LOC = P138 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
NET "SUM[15]" LOC = P137 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
NET "SUM[16]" LOC = P134 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
NET "SUM[17]" LOC = P133 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
NET "SUM[18]" LOC = P132 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
NET "SUM[19]" LOC = P131 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
NET "SUM[20]" LOC = P43 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
NET "OUT1" LOC = P44 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
NET "OUT2" LOC = P45 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
NET "OUT3" LOC = P46 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
NET "OUT4" LOC = P47 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
NET "OUT5" LOC = P48 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ; 
NET "OUT6" LOC = P50 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
NET "OUT7" LOC = P51 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
NET "OUT8" LOC = P55 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
NET "OUT9" LOC = P56 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ; 
NET "OUT10" LOC = P74 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
NET "OUT11" LOC = P75 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
NET "OUT12" LOC = P78 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
NET "OUT13" LOC = P79 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
NET "OUT14" LOC = P80 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
NET "OUT15" LOC = P81 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
NET "OUT16" LOC = P82 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
NET "OUT17" LOC = P83 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
NET "OUT18" LOC = P84 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
NET "OUT19" LOC = P85 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
NET "OUT20" LOC = P87 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
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  • \$\begingroup\$ What do you mean by "doesn't seem to be working"? Are you getting error messages? \$\endgroup\$ – Elliot Alderson Aug 8 '18 at 16:42
  • \$\begingroup\$ @ElliotAlderson when I try to program the board, the programming fails (the actual compiling works just fine) and it says "Configuration failed". \$\endgroup\$ – heather Aug 8 '18 at 16:44
  • \$\begingroup\$ Do you change the LOC = PXX as well, to valid locations? \$\endgroup\$ – Ale..chenski Aug 8 '18 at 17:15
  • \$\begingroup\$ @AliChen the LOC = PXX points to a valid location, yes. \$\endgroup\$ – heather Aug 8 '18 at 17:17
  • \$\begingroup\$ And when you pull out the final FPGA routing map, do you have the signals hooked up to your designated LOCs? \$\endgroup\$ – Ale..chenski Aug 8 '18 at 17:20
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Okay, it looks like the question is "how to program FPGA and make the Xilinx ISE toolchain to work.

First, start with something extremely simple, like a clock-in, a push button, a 32-bit counter (Verilog code), and a LED. All external elements are available on the Mimas development board. Make something like connect bit[26] to LED output and "if the button is pushed", start counting. It should give you about 1 s flash rate (with 100 MHz clock input).

Then use their .ucf file for the selected button, clock (inputs) and for selected LED (output).

Then compile your code ensuring that there are no errors (or warnings). The compiler would likely optimize out all improperly connected nets, and you might end up with empty design.

Implement the design; Translate-Map-Place-Route will happen. Again, watch for any errors and correct them.

In "View/Edit Routed Design (FPGA Editor)" you should see connections and LOC occupied with placed components/pads.

When selecting/configuring the project, make sure you select right part for it.

Only after you master the basic tool functionality (compile/implement/program) and make the LED blinking, you can start your more complex design and wonder where your vectors go.

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  • \$\begingroup\$ For the record, I've gotten it working with a blinking LED in the past. \$\endgroup\$ – heather Aug 8 '18 at 18:01
  • \$\begingroup\$ @heather, fine, then you should be able to see the routed design, with traces/interconnects in FPGA editor. I see no traces in your picture, unless you disabled their view. \$\endgroup\$ – Ale..chenski Aug 8 '18 at 18:03
  • \$\begingroup\$ Well, here is the RTL schematic, clearly there's some connections. \$\endgroup\$ – heather Aug 8 '18 at 18:06
  • \$\begingroup\$ @heather, these are RTL connections. They should be translated, mapped, and routed to physical CLBs inside FPGA. The FPGA Editor should be able to display actual routing. Does it? Also, could you present the top design summary, I/O utilization, FF and CLB used, Clock managers used, etc. Form the front page of ISE tool? \$\endgroup\$ – Ale..chenski Aug 8 '18 at 18:09
  • \$\begingroup\$ Your syntax looks fine... Make sure you included the UCF file in your PAR. Check the Post PAR report to confirm placement as you intended. \$\endgroup\$ – CapnJJ Aug 10 '18 at 18:21

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