4
\$\begingroup\$

This is the circuit I am currently analyzing: (link to LTSpice file)

enter image description here

I am trying to predict each stage closed loop gain and overall gain (with all loops closed).

First thing I did is calculate DC conditions in circuit for given parameters and then started dealing with feedback of each circuit. Also, at beginning, I connected each sub-circuit separately to a source, to make things easier.

schematic

simulate this circuit – Schematic created using CircuitLab

FIGURE A:

\$r_e = 43\Omega\$, \$\beta = 250\$, \$I_c = 600 \mu A\$, \$r_\pi = 10.8k\Omega\$, \$A_{ol} = 387\$

\$r_e = 26mV/I_e\$, \$r_\pi = r_e *(\beta + 1)\$, \$A_{ol} = \frac{(R_2 + R_1||R_\pi)||R_3}{r_e}\$ (NFB loading included)

I defined closed loop equation from KCL $$ \frac{V_{IN}-V_B}{R_1} - \frac{V_{OUT}-V_B}{R_2} - \frac{V_B}{r_\pi} = 0 $$ and got

$$ A_{CL(Q1)} = \frac{V_{OUT}}{V_{IN}} = \frac{R_2}{R_1} - \frac{V_B R_2(R_2 r_\pi - R_1 r_\pi + R_1 R_2)}{V_{IN}R_1 R_2 r_\pi} = 30.4 $$

In LTSpice I measured \$ \frac{V_{OUT}}{V_{IN}} = 30.3 \$, so I got pretty close with upper equation.

FIGURE B:

\$r_e = 43\Omega\$, \$\beta = 250\$, \$I_c = 592 \mu A\$, \$r_\pi = 66.2k\Omega\$, \$A_{ol} = 63 \$

\$r_e = 26mV/I_e\$, \$r_\pi = (R_9+r_e) *(\beta + 1)\$, \$A_{ol} = \frac{(R_7 + R_1||R_\pi)||R_5}{(R_9+r_e)}\$ (NFB loading included)

I defined closed loop equation from KCL $$ \frac{V_{IN}-V_B}{R_1} - \frac{V_{OUT}-V_B}{R_7} - \frac{V_B}{r_\pi} = 0 $$ and got

$$ A_{CL(Q2)} = \frac{V_{OUT}}{V_{IN}} = \frac{R_7}{R_1} - \frac{V_B R_7(R_7 r_\pi - R_1 r_\pi + R_1 R_7)}{V_{IN}R_1 R_7 r_\pi} = 22.4 $$

In LTSpice I measured \$ \frac{V_{OUT}}{V_{IN}} = 21.3 \$. Not so close to calculated value as for Figure A, but close enough for me.

FIGURE C: (here things aren't as they should be - as was measured from LTSpice)

Main thing here was to predict overall gain of circuit from Figure C. I thought I would achieve this by multiplying each sub-circuits closed loop (active) gain and also multiplying each sub-circuit's input gain (passive - smaller than 1), which comes into place due to finite input resistance and non-zero output resistance of each BJT. Like so:

$$ A_{CL(OVERALL)} = A_{P(Q1)} * A_{CL(Q1)} * A_{P(Q2)} * A_{CL(Q2)} = 354 $$

where

$$ A_{P(Q1)} = \frac {r_{\pi(Q1)}}{R1+r_{\pi(Q1)}} = 0.65 $$ $$ A_{P(Q2)} = \frac {r_{\pi(Q2)}}{((R_2 + R1||r_{\pi(Q1)})||R3)+r_{\pi(Q2)}} = 0.80 $$

In LTSpice, I measured \$ A_{CL(OVERALL)} = 1135 \$. As you can see, measured value is at least 3x bigger compared to what I calculated! This is a huge difference that cannot be accepted. So, when both sub-circuits are combined, something happens that I didn't manage to predict. Something must greatly be wrong with my calculations, otherwise such enormous error wouldn't take place in this example.

Can anyone tell/explain me, where did I go wrong, when analyzing this specific circuit? Can anyone spot the mistake(s) I have made?

\$\endgroup\$
  • \$\begingroup\$ You omitted the effects of input, output impedance reduction from negative feedback. I get 14x50=700 gain \$\endgroup\$ – Tony Stewart Sunnyskyguy EE75 Aug 9 '18 at 14:32
  • 1
    \$\begingroup\$ that was @5V but @ 12V , gain is ~19*61 = 1160 . If you wanted to build this for large signal output, then you would add 22k to 50k across Vbe2 to increase Vce to V+/2 \$\endgroup\$ – Tony Stewart Sunnyskyguy EE75 Aug 9 '18 at 14:56
  • \$\begingroup\$ @TonyEErocketscientist Can you explain how you got gain of 1160? \$\endgroup\$ – Keno Aug 9 '18 at 15:59
  • 1
    \$\begingroup\$ Good, next In my simulation when stable increase C to 1mf in 1st stage Vout to probe. Then reduce load from 1M down . As this interface load attenuates Av1 at the same time increases feedback gain on Av2 and output won’t change , hence the paradox of constant gain until to change the DC bias current that is or quiescent Vc operating point then gain rises somewhat with base current as you expect . Then if done in Q1 you also lower Zout1 \$\endgroup\$ – Tony Stewart Sunnyskyguy EE75 Aug 9 '18 at 22:25
  • 1
    \$\begingroup\$ Your circuit does not have any overall feedback loop, only local negative feedback loops. So the overall voltage gain cannot be called "closed-loop gain". \$\endgroup\$ – G36 Aug 10 '18 at 16:45
3
\$\begingroup\$

We have this circuit

schematic

simulate this circuit – Schematic created using CircuitLab

First, we need to find the voltage gain for a second stage.

This gan will be equal to

$$A_{V2} \approx \frac{R_{C2}||R_L||R_{B2}}{r_{e2}+R_{E2}} \approx \frac{16.3\textrm{k}\Omega}{263\Omega} \approx 62 V/V$$

To find the voltage gain for a first stage we need to know the input impedance of a second stage.

And we can find it using the Miller theorem How does a Miller cap physically create a pole in circuits?

$$R_{in2} \approx \frac{R_{b2}}{A_{V2}}|| \left(\beta2\cdot (r_{e2}+R_{E2}) \right) \approx 3.36\textrm{k}\Omega $$

Try to derive the full expression for \$R_{in2}\$

Now the first stage voltage gain:

$$A_{V1} \approx \frac{R_{C1}||R_{in2}||R_{B1}}{r_{e1}} \approx \frac{2.8\textrm{k}\Omega }{43\Omega} \approx 65 V/V$$

And the input impedance:

$$R_{in1} \approx \frac{R_{b1}}{A_{V1}}|| \left(\beta1\cdot r_{e1}\right) \approx 2.57\textrm{k}\Omega $$

So the overall voltage gain is:

$$A_V =\frac{R_{in1}}{R_g + R_{in1}}\cdot A_{V1}\cdot A_{V2} \approx 1180 V/V $$

Do you see your mistake now?

EDIT

And you can use LTspice to confirm this results. And the easiest will be if you use AC Analysis. And set AC source to 1V. Thanks to this you will get the result directly in V/V.

See the example

enter image description here

As you can see I set the AC source at 1V and the voltage gain of the first stage alone is V(vin2)/V(vin1) equal to 63.4 V/V.

And by using the AC analysis you can plot Rin, Rout widout any problem.

For example, the Rin2 is V(vin2)/I(C2)

enter image description here

enter image description here

| improve this answer | |
\$\endgroup\$
  • \$\begingroup\$ Well done. I see what you mean by this method of impedance ratios \$\endgroup\$ – Tony Stewart Sunnyskyguy EE75 Aug 11 '18 at 4:11
  • \$\begingroup\$ I doubt I would ever find this term \$ \frac{R_b}{A_V} \$ for \$ R_{in} \$ by myself, though. So, you must be pretty experienced in defining circuit parameters, am I right? \$\endgroup\$ – Keno Aug 11 '18 at 8:25
  • \$\begingroup\$ @Keno You do not recognize the Miller theorem at work? electronics.stackexchange.com/questions/336474/… If you connect a resistor between input and the output of an inverting amplifier with a gain of A. This resistor will now be seen as R/(A + 1). And in your circuit, R2 and R7 are the resistors that were connected between the output and the input of an inverting amplifier. \$\endgroup\$ – G36 Aug 11 '18 at 13:39
  • \$\begingroup\$ I mean, did you found that formula yourself by using Miller's Theorem? Or did you found it somewhere else? Because I doubt I would have managed to define it myself. \$\endgroup\$ – Keno Aug 11 '18 at 14:21
  • \$\begingroup\$ I wrote them by inspection. It is quite easy. Notice that thanks to the Miller's Theorem we can look at R2 as a resistor R2/(1+AV) connected between base and ground. And at the output, as R2 resistor connected between collector and ground. Therefore Rin1 = R2/(1+AV)||r_pi and the voltage gain AV = (Rc||R2||Rin2)/re \$\endgroup\$ – G36 Aug 11 '18 at 14:34
1
\$\begingroup\$

You've got about 10 volts across each transistor Vce. The Ic is 0.5mA. The 'reac' is 26/0.5 = 52 ohms.

Divide the Rc of the first stage, 18,000/52 ~~ 360X gain, ignoring EarlyVoltage and being loaded by the 2nd stage.

The second stage has total reac of 220+52 = 270 ohms. The gain will be 18,000 / 270 = 54x.

Note: I'm ignoring how Stage2 Rin loads Stage1.

| improve this answer | |
\$\endgroup\$
  • \$\begingroup\$ You only mentioned open loop gains of each Q, individually. This is easy to achieve. It is harder to explain, why closed loop gain cannot be calculated with my equations. \$\endgroup\$ – Keno Aug 10 '18 at 8:52
  • \$\begingroup\$ @analogsystemrf , you can measure Zout and tinyurl.com/y96cbh8c by opening stages (pull C up) and loading AC coupled 1M probe to drop voltage 50%. (and increasing f or C) then measure Zin2 by reducing 1M probe R to get same AV1 gain when connected. \$\endgroup\$ – Tony Stewart Sunnyskyguy EE75 Aug 10 '18 at 12:42
  • 1
    \$\begingroup\$ You made your mistake there when you said there is 10V = Vce across each transistor. You have approx. 10.8V =V_RC and 1.2V = V_CE. \$\endgroup\$ – Keno Aug 10 '18 at 16:29
  • 1
    \$\begingroup\$ @ Keno Yes. Given the ratio of Rb to Rc is only about 10:1, I knew the collector-emitter voltage would be low. I did all the Ic computations based on 10volts across the 18Kohm Rc. Thank you. \$\endgroup\$ – analogsystemsrf Aug 11 '18 at 3:42

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.