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I was given this power supply circuit, please see the image. The problem I'm having is when I connect the 10ohm load (solenoid valve), there is a large ripple when I scope the output. I have provided a few images to show you what I'm dealing with. I have tried adding different size caps in parallel with R23. Any help would be very much appreciated.

Power Supply Image 1: The Power Supply circuit

Power Supply Switch Image 2: Power Supply Switching circuit

Pulse With No load
Image 3: Pulse without 10ohm load

With 10ohm load Image 4: Pulse with 10ohm load

I have other images of the different caps used, 1nF and 0.1uF. Both of these in parallel with R23 made the ripple MUCH MUCH worse!!

Thank you all

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    \$\begingroup\$ Can you edit the schematics ? It's hard to see them. \$\endgroup\$
    – Long Pham
    Aug 9, 2018 at 16:30
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    \$\begingroup\$ If you're trying to provide feedforward compensation, you should put a cap in parallel with R21, not R23. \$\endgroup\$
    – The Photon
    Aug 9, 2018 at 16:39
  • \$\begingroup\$ I updated the images, sorry for the duplicate image can't remove it. @The Photon I will give that a try..I have also try a cap in parallel with R13 and R182 \$\endgroup\$
    – hfbroady
    Aug 9, 2018 at 16:44
  • \$\begingroup\$ @The Photon It's between the 2 transistors. Also, the cap in parallel with R21 didn't make it better, made more ripple, but less than the other ones(R23). I have images if you want to see them. \$\endgroup\$
    – hfbroady
    Aug 9, 2018 at 16:56

1 Answer 1

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The way to compensate these loops is to add a capacitor across the transistor section OR put a capacitor R21. This may cut your response time, but you can't have both no ripple and response without drastically changing the design.

enter image description here

If you do it right you'll run a spice simulation (usually I do this for people, but I'm way to lazy right now), usually you'll see a Q resonant point in the higher end of the frequency range like the picture shown below. If you do a spice simulation, make sure you simulate the inductance of any wires or large traces, or your simulation will not match the real world.

If you don't run a spice simulation, you could run an FFT on your scope data, see the point of resonance and insert a LPF pole before the resonance Q point. Compensating these loops is not intuitive because of their closed loop nature.

If you plan on using this supply over a large range of DC output values, the Q point will change for each DC value because of the transistors.

enter image description here

Source: https://www.researchgate.net/publication/2983401_A_Low-Dropout_Regulator_for_SoC_With_-Reduction/figures?lo=1

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