I'm doing a DC-DC buck converter routing, using TPS62130. As known, the key point to route a DC-DC converter is to reduce the current loop area. In my design, I have a dedicated ground plane, so I have two choices to close the current loop:

  1. The left one, the loop is closed on the top layer.
  2. The right one, the loop is closed through vias, and the current flows on the ground plane and return through the thermal vias back to the PGND of the chip.

In the graph, the biggest component is the output inductor, and there are two output capacitors in parallel at the right end of the inductor. The only difference is: The left one, no current will flow on the ground plane. But the right one, the current will go through vias and flow on ground plane, then return to top layer. Which one is better?

enter image description here

  • \$\begingroup\$ Better how? Lower noise on the rails? \$\endgroup\$
    – MIL-SPEC
    Aug 10 '18 at 7:32
  • 1
    \$\begingroup\$ it's not 'to reduce the current loop', it's to reduce the loop area of the changing current. So you need to include the input and output capacitors, as well as the inductor and switch, in your considerations. \$\endgroup\$
    – Neil_UK
    Aug 10 '18 at 7:52
  • \$\begingroup\$ @MIL-SPEC: Such as low noise. \$\endgroup\$
    – diverger
    Aug 10 '18 at 8:03
  • \$\begingroup\$ @Neil_UK: Yes, there indeed has output capacitor. \$\endgroup\$
    – diverger
    Aug 10 '18 at 8:05
  • \$\begingroup\$ @Neil_UK: More precisely, it won't be reduce the inductance of the current loop? \$\endgroup\$
    – diverger
    Aug 10 '18 at 8:12

I'd prefer the one on the left. Although a ground plane provides a good, low impedance path for return currents, keeping those ripple currents off of the ground plane will reduce the noise seen by other parts of the circuit. I'd go a step farther and connect the input cap to the output caps on the top layer. Remember that you have two current loops in any switching supply, depending on which phase of the cycle you're in.


Always refer back to TI's design. The current will return using the multiple vias to the top and bottom layer.


Page 14.


  • \$\begingroup\$ The reference design use top layer as GND and PWR plane. And the entire current loop is on the top layer, no vias to other layer. \$\endgroup\$
    – diverger
    Aug 10 '18 at 10:45
  • \$\begingroup\$ I double checked again. It actually uses 2 layers for the ground return. \$\endgroup\$
    – Jason Han
    Aug 14 '18 at 1:48

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