I just ran the DRC check in Altium for my PCB and I get errors on trace width for every trace segments on the board.
What is the reason for this ? It generated thousands of errors even tho all the traces are 4 to 5 mils wide.
All tracks width rules are set to >= 4 mils
This is the error message I get under "Rule Violations" :
Clearance Constraint (Gap=3.5mil) (All),(All)
Clearance Constraint: (Collision < 3.5mil) Between Track (52761.3mil,31343.2mil)(52769.499mil,31343.2mil) on Solder Side And Arc (52769.499mil,31340.4mil) on Solder Side
Edit: It also affects trace much much larger than 3.5 mils