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I just ran the DRC check in Altium for my PCB and I get errors on trace width for every trace segments on the board.

What is the reason for this ? It generated thousands of errors even tho all the traces are 4 to 5 mils wide.

All tracks width rules are set to >= 4 mils

This is the error message I get under "Rule Violations" :
Clearance Constraint (Gap=3.5mil) (All),(All)
Clearance Constraint: (Collision < 3.5mil) Between Track (52761.3mil,31343.2mil)(52769.499mil,31343.2mil) on Solder Side And Arc (52769.499mil,31340.4mil) on Solder Side


enter image description here enter image description here

Edit: It also affects trace much much larger than 3.5 mils

enter image description here

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  • \$\begingroup\$ What is the actual error message? \$\endgroup\$
    – Daniel
    Commented Aug 10, 2018 at 21:32
  • \$\begingroup\$ Are those white rings vias? or some other thing you've placed on the corners? You wouldn't normally see rings like that at a bend in a track. \$\endgroup\$
    – Peter Bennett
    Commented Aug 10, 2018 at 21:34
  • \$\begingroup\$ @Daniel I added it to the question. and PeterBennett Nope, these are only routed, no vias, no nothing, pure corners \$\endgroup\$
    – GmodCake
    Commented Aug 10, 2018 at 21:35
  • \$\begingroup\$ Well, the error message says the violation is between a track and an arc - so somehow arcs were placed where the tracks bend. \$\endgroup\$
    – Peter Bennett
    Commented Aug 10, 2018 at 21:37
  • \$\begingroup\$ Are the elements you're connecting on the same nets? (Are they connected to the same net name in your schematic?) \$\endgroup\$
    – Daniel
    Commented Aug 10, 2018 at 21:38

3 Answers 3

Reset to default
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It turns out it was in the clearance rule I selected "Any nets" by mistake which meant the rule was applied to any segment no matter what net it is from, changing it back to "Different nets only" fixed it.

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The image you've attached is for Minimum Clearance between components. There should be another dialog that defines the minimum and maximum trace widths. Double check that they are correct.

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  • \$\begingroup\$ It doesn't work not matter what I put, all my tolerance, clearance, trace width are >4 mils \$\endgroup\$
    – GmodCake
    Commented Aug 12, 2018 at 6:29
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What ARCs is it referring to? From your picture, I can't see any.

Use the PCB Filter "IsArc" to see where these mystery geometries are coming from.

Did you accidentally convert your vias to free pads? I could see that causing some issues for the DRC.

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