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If I have the following verilog module definition:

module foo (
  input a,
  output b
  );

  assign b = !a;

endmodule

And then I instantiate it within another module like so

module bar (
  input c,
  output d
  );

  foo foo0 (
    .a(c),
    .b(!d) //note the not operator
  );

endmodule

I looked at the EBNF syntax definition for Verilog and it showed expressions as valid arguments for port assignment.
Will this do what I want (i.e. act as a passthrough—outputting c)? Or does verilog not allow operators other than concatenation for port assignment?

I realize this example is contrived, but my project has a decent amount of code so I didn't want to upload/explain all of it unless necessary.

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  • \$\begingroup\$ What happened when you ran a simulation of this code? \$\endgroup\$ – Elliot Alderson Aug 11 '18 at 1:37
  • \$\begingroup\$ @ElliotAlderson I did not; I suppose I probably should've \$\endgroup\$ – rfoster Aug 11 '18 at 1:38
  • \$\begingroup\$ @ElliotAlderson alright I attempted to simulate it with Verilator; that failed when the ! operator was present and succeeded when not present (although it didn't do what I wanted obviously). I also attempted to use XST to synthesize the files and it failed as well. Looks like I should just make a temporary wire \$\endgroup\$ – rfoster Aug 11 '18 at 2:12
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This is legal for input port connections, but output ports can only be connected to nets and/or variables, or a concatenation of those. See section 23.3.3.3 Port connection rules for nets with built-in net types of the 1800-2017 LRM.

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