If I have the following verilog module definition:
module foo ( input a, output b ); assign b = !a; endmodule
And then I instantiate it within another module like so
module bar ( input c, output d ); foo foo0 ( .a(c), .b(!d) //note the not operator ); endmodule
I looked at the EBNF syntax definition for Verilog and it showed expressions as valid arguments for port assignment.
Will this do what I want (i.e. act as a passthrough—outputting c)? Or does verilog not allow operators other than concatenation for port assignment?
I realize this example is contrived, but my project has a decent amount of code so I didn't want to upload/explain all of it unless necessary.