I am trying to design PCB with 85 MHz signal traces between IC and connector (the FPGA board will be connected to this connector). This connection contains 28 data signals and one clock signal. I wonder if in this case I should try to match the length of the signal paths or rather leave them as you can see in the first picture.

Without matching, the longest path is currently ~50 mm and the shortest ~15 mm. Of course, I can bring the connector closer to the IC, but at the moment I have left some room to try and match the length. However, I think the ratio between the shortest and the longest will always be at least 1:2.

With this number of connections it's a bit difficult to fit these curved tracks, but I can try. If all the paths could finally be matched to one another, the connector would be moved away from the IC, can such unusual paths have any negative impact on the project?

option 1 - "straight" traces option 2 - "curved" traces


2 Answers 2


The difference in propagation delay between 15mm and 50mm of PCB trace is less than 250ps (assuming 150mm/ns VoP), and the clock period here is just under 12ns. So no big deal. The only thing I might do is increase your clock length to match the longest data trace, then document the maximum skew (250ps) to the FPGA designer, who can probably play with the clock phase to deliver the best possible setup and hold margins at the destination.

If it were me, the FPGA clock output would be a DDR register toggling with the data, and I'd invert it to put the rising edge right in the middle of the data eye.

I am assuming the FPGA is the transmitter because I see no series termination resistors on the IC on your layout.

  • \$\begingroup\$ Thanks, I'm less worried now. And I will design FPGA core :) The FPGA is the receiver, data is from the deserializing IC. So I understand I have missing series termination resistors... Any simple way to calculate their values? \$\endgroup\$
    – bLAZ
    Commented Aug 11, 2018 at 13:20
  • \$\begingroup\$ A series termination matches the driver to the transmission line (PCB trace impedance.) Say you control your traces to be 60 ohms by setting their widths correctly, and your deserializer has output drivers with an on resistance of about 10 ohms or less, you might pick a 47 ohm resistance. Probe at an FPGA pin with a low capacitance scope probe and adjust if there's too much over/undershoot. Build the FPGA design with timing constraints before freezing your board layout - you may need to add length to the clock path. \$\endgroup\$
    – amb
    Commented Aug 11, 2018 at 13:36

You need to count a delay of 1ns/15cm (half the speed of light) for your PCB signals. Your clock is about 11ns, the delay in the wires is probably not an issue.

You do need to check your overall timing budget of course and make sure that it works over temperature too.

I would worry more about grounds in your connector and near to your clock. Apparently every signal is next to a ground in your connector, so your fine there. For the clock, make sure to keep a gap with the other signals. The gap should be three times your clock signal's width - or add a ground signal on both sides of your clock.

If your timing analysis shows that you have an issue, adjusting the length of some wires can be your allie. If you need 1ns of delay for example, you can add 15cm to your trace.


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