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A few years ago I had to design a board that uses the NXP LPC1769 MCU and had Ethernet connectivity. I was in need of a PHY chip and the LAN8720 was choosen.

During design however, I noticed that NXP in their development boards use an inverting buffer on the REFCLOCK signal (see here, U9). I searched the datasheet, but I couldn't really understand the reason for this inverter. Finally I decided to follow their advice and also use the inverter. The board worked perfectly, as many more following designs did.

Now we are migrating to the STM32F427 MCU, and again I need Ethernet connectivity. I plan to use again the LAN8720 PHY, but I am confused about whether I should invert the REFCLOCK signal again.

Since I didn't understand why it was needed in the first case, I am not sure what to look for now to ensure whether it is needed or not.

Why this inverter was used? Where one can find information on the datasheet about this? And most importantly how can I know whether I need it on the new design?

Note: Space is at a premium for my new design, so eliminating even such a small part will be beneficial. I wouldn't really like to add it to the design just for a trial-and-error approach, only to find out it needs bypassing...

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The answer is on page 29 of the LAN8720A datasheet: The REF_CLK Out Mode is not part of the RMII Specification. Timing in this mode is not compliant with the RMII specification. To ensure proper system operation, a timing analysis of the MAC and LAN8720 must be performed.

I would bet that NXP did that analysis and needed to invert the clock to achieve good timing margins. The propagation delay of the LVC inverter, and maybe even the RMII trace lengths, will have been part of that process.

The STM32F427 timing requirements and characteristics should be very similar to the LPC1769; RMII is RMII... But I would do a fresh analysis if I were you!

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  • \$\begingroup\$ And I bet the analysis includes actual measuring the signals? Or is there any other way to calculate it during design? \$\endgroup\$ – Fotis Panagiotopoulos Aug 11 '18 at 13:05
  • \$\begingroup\$ I would say not. Timing analysis is usually performed before layout with the outcome driving constraints through to the board design e.g. path length matching requirements. If you are not familiar with the process, you will need to learn how to do it, but it's not difficult. \$\endgroup\$ – amb Aug 11 '18 at 13:28
  • \$\begingroup\$ I am not familiar with the process. Can you recommend me any resources to study on this matter? \$\endgroup\$ – Fotis Panagiotopoulos Aug 11 '18 at 14:41
  • \$\begingroup\$ It's remarkably hard to find a concise tutorial! Why not start by looking at this tool which is a decent (free) timing diagram editor; use it to draw the timing of the RMII and relevant clock signals, taking into account all the requirements and characteristics from the datasheets. \$\endgroup\$ – amb Aug 11 '18 at 15:13
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There is an interesting part in the LAN8720 datasheet, page 29 bottom:

The REF_CLK Out Mode is not part of the RMII Specification. Timing in this mode is not compliant with the RMII specification. To ensure proper system operation, a timing analysis of the MAC and LAN8720 must be performed.

In other words, the problem is up to the pcb desinger...

If you look at the LPCXpresso schematic, there is not just the inverter but also an (unpopulated) footprint for a bypass resistor.

I suggest using the same approach, so you can either populate the inverter or the resistor in the final product, depending on testing results.

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