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I am attempting to create a working JK flip flop using gate level description in verilog. Although, the design is successfully compiled and simulated, the outputs to the FF are always unknown.

Please note that the design is a modified 'SR-Latch with enable' design (which is known to operate correctly) with the outputs tied to the inputs.

module JK_FlipFlop(input clk, J, K, output Q, Q_not);
    wire    wl0, wl1;

    nand    g0 (wl0, clk, J, Q_not),
            g1 (wl1, clk, K, Q),
            g2 (Q, wl0, Q_not),
            g3 (Q_not, wl1, Q);
endmodule

I have also tried other implementation of the JK Flip-flops using gate level description and the outcome is always the same; with the outputs being unknown.

The test bench used is shown below:

module test_JKFF;
   reg   clk;
   reg   J;
   reg   K;   
   wire  Q;
   wire  Q_not;   
   // Instantiate the Unit Under Test (UUT)
   initial begin
   // Initialize Inputs
       J = 0;
       K = 0;
       fork
       #5 K = 1;
       #15 J = 1;
       #15 K = 0;
       #25 J = 1;
       #25 K = 1;
       #50 J = 0;
       #50 K = 0;
       #60 K = 1;
       #70 J = 1;
       #70 K = 0;
       #80 K = 1;
       clk = 0;
       join
      // Wait 100 ns for global reset to finish
       #100;
    end

    JK_FlipFlop UUT(clk, J, K, Q, Q_not);

    always #5 clk=!clk;

endmodule

Therefore, any insight that anyone may be able to provide in relation to this question would be very much appreciated.

Thanks

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  • \$\begingroup\$ Try adding a little delay to each gate, and allow plenty of time between transitions of the J, K inputs and transitions of the clk. \$\endgroup\$ – Elliot Alderson Aug 12 '18 at 12:57
  • \$\begingroup\$ You have to add an initial state. e.g. use 'force' in an initial statement. \$\endgroup\$ – Oldfart Aug 12 '18 at 13:02
  • \$\begingroup\$ Thanks @ElliotAlderson for your suggestion; I will give that a try. \$\endgroup\$ – aLoHa Aug 12 '18 at 13:15
  • \$\begingroup\$ @Oldfart can you please elaborate on how to use 'force' in an initial statement, as I'm a little unfamiliar with that method? \$\endgroup\$ – aLoHa Aug 12 '18 at 13:15
  • \$\begingroup\$ @aLoHa, What do you mean by "the design is successfully simulated, the outputs to the FF are always unknown"? Why is that successful? Can you provide the stimulus you gave to the design? \$\endgroup\$ – dave_59 Aug 12 '18 at 16:59
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Well, that certainly isn't what I would call a JKFF. I normally reserve that term for a true master-slave edge-triggered device. With your circuit, when J, K and clk are all high, the outputs will simply oscillate as fast as the simulator allows. (Actually, it will probably just tell you that no stable state can be found.)

There is no combination of inputs that will force your circuit into a known state. The usual solution to this is to make g2 and g3 into 3-input gates. Label the extra input on g2 as set_l (active-low direct-set input) and the extra input on g3 as reset_l. These will be able to force the state of Q and Q_not when they are asserted low, regardless of the state of the other inputs.

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  • \$\begingroup\$ :) To be honest, I get the same response for the master-slave edge triggered versions too. But, thank you for your suggestion. It is very much appreciated and I will be giving it a go. \$\endgroup\$ – aLoHa Aug 13 '18 at 22:20
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With regards to the question posed, i.e, "Is it possible to create a working JK-flip flop using gate level description in Verilog?", the answer is "Yes"!!

It can be accomplished using a gate level description of a D-type edge triggered flip flop with reset as intimated by @DaveTweed. This ensures that Q and Q_not are set a value, as opposed to having unknown states, prior to being provided a stimulus.

Please see below for complete example of module:

module DTFF_reset(output Q, Q_not, input D, clk, reset);
    wire    wl0, wl1, wl2, wl3;

    nand    g0 (wl0, wl1, wl3),
            g1 (wl1, clk, wl0, reset),
            g2 (wl2, clk, wl1, wl3),
            g3 (wl3, D, wl2, reset),
            g4 (Q, wl1, Q_not),
            g5 (Q_not, wl2, Q, reset);
endmodule


module JK_FF_reset(output Q, input J, K, clk, reset);
    wire    K_not, qnot, wl0, wl1, wl2;

    // instantiate gates
    not     g0 (K_not, K);

    and     g1 (wl0, J, qnot),
            g2 (wl1, K_not, Q);

    or      g3 (wl2, wl0, wl1);
    // instantiate D-Flip-flop module
    DTFF_reset D0 (q, qnot, wl2, clk, reset);
endmodule
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-1
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When somebody explains how a Flip-Flop works (e.g. Built from two NAND or two NOR gates) they start with: "Lest assume this output is LOW".

Inevitable there is the question:"But how does it start up" at which point supply noise and other factors are brought up to explain that it will get into one of two states.

But in simulation there is no supply noise of 'other factors' so you have to somehow get the system in a stable state.

This does the same:

initial
begin
  J=1'b0; 
  K=1'b0;
  // System is undefined
  // Force a state 
  force Q = 1'b1;
  #1 release Q;

end
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  • \$\begingroup\$ No, you don't "have to", and I think it is a very bad idea to do so. You should let all of the flip-flops and latches wake up in an unknown state, as they will in the real world. If you can't control the circuit and get it into a known state then you have a problem. There's nothing wrong with having unknown outputs for a few clock cycles. \$\endgroup\$ – Elliot Alderson Aug 12 '18 at 16:35
  • \$\begingroup\$ @ElliotAlderson That statement is correct IF the circuit resolves itself in due time. However here we have a situation where no matter how long you wait the circuit will never get into a know state unless you force it. The OP is not working with "standard" Verilog code. \$\endgroup\$ – Oldfart Aug 12 '18 at 16:40
  • \$\begingroup\$ Thanks for elaborating. It is very much appreciated and I will also give your suggestion a try. \$\endgroup\$ – aLoHa Aug 13 '18 at 22:23
  • \$\begingroup\$ @ElliotAlderson, out of curiosity, what sort of delays would you apply to the gates and how much time would you allow between the transitions of the inputs? \$\endgroup\$ – aLoHa Aug 13 '18 at 22:40

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