I am attempting to create a working JK flip flop using gate level description in verilog. Although, the design is successfully compiled and simulated, the outputs to the FF are always unknown.
Please note that the design is a modified 'SR-Latch with enable' design (which is known to operate correctly) with the outputs tied to the inputs.
module JK_FlipFlop(input clk, J, K, output Q, Q_not); wire wl0, wl1; nand g0 (wl0, clk, J, Q_not), g1 (wl1, clk, K, Q), g2 (Q, wl0, Q_not), g3 (Q_not, wl1, Q); endmodule
I have also tried other implementation of the JK Flip-flops using gate level description and the outcome is always the same; with the outputs being unknown.
The test bench used is shown below:
module test_JKFF; reg clk; reg J; reg K; wire Q; wire Q_not; // Instantiate the Unit Under Test (UUT) initial begin // Initialize Inputs J = 0; K = 0; fork #5 K = 1; #15 J = 1; #15 K = 0; #25 J = 1; #25 K = 1; #50 J = 0; #50 K = 0; #60 K = 1; #70 J = 1; #70 K = 0; #80 K = 1; clk = 0; join // Wait 100 ns for global reset to finish #100; end JK_FlipFlop UUT(clk, J, K, Q, Q_not); always #5 clk=!clk; endmodule
Therefore, any insight that anyone may be able to provide in relation to this question would be very much appreciated.