# Finding drain voltage for a resistor loaded CMOS inverter with 0V at input terminal

Introduction: The following example is from the textbook Sedra/Smith Microelectronic Circuits. It is stated in the solution to this example that since both $Q_n$ and $Q_p$ are both matched and $|V_{GS}|= 2.5V$ then $v_o$ must be 0V, thus both transistors will be in the saturation region. It is this conclusion that I wanted to investigate. My overall question is why does $v_o$ have to be 0V?

Used Equations:

Saturation current equation for NMOS:

$i_D = \frac{1}{2}k_n^\prime(\frac{W}{L})(V_{GS} - V_{tn})^2$

Saturation current equation for PMOS:

$i_D = \frac{1}{2}k_p^\prime(\frac{W}{L})(V_{SG} - V_{tp})^2$

Condition for ON:

NMOS- $V_{GS} \geq V_{tn}$ PMOS- $V_{SG} \geq V_{tp}$

Condition for Saturation:

NMOS- $V_{DS} \geq V_{GS} - V_{tn}$ PMOS- $V_{SD} \geq |V_{SG} - V_{tp}|$

Condition for Triode:

NMOS- $V_{DS} < V_{GS} - V_{tn}$ PMOS- $V_{SD} < |V_{SG} - V_{tp}|$

Solution Method:

Since I already knew the answer to this problem then I was going to work backwards to prove that the only possible solution to this circuit is for both $Q_n$ and $Q_p$ to be in saturation. My method is to show that both the transistors can not be in triode\triode, triode\saturation, or saturation\triode.

Solution:

Since the saturation current equations for both transistors in saturation are independent of $V_{DS}$ and are perfectly matched then both transistors have the same current passing through them. In order for this to be true that means that no current is going through the resistor which results in $v_o$ being at 0V. Now the problem is tackling other operative modes for the transistors.

For triode\triode it can be found that for $Q_n$ to be in triode $V_D < -1$ and for $Q_p$ to be in triode $V_D > 1$. Since the drains of the transistors are connected then there is no V_D such that it can satisfy both inequalities at the same time. This means that triode\triode is not possible.

Now where I am stuck is showing that triode\saturation and saturation\triode also are not possible, but I have yet to find a way. This is the underlying question to my solution method.

Is there a simpler solution to this problem or is there a way to show that triode\saturation and saturation\triode are invalid?

• Both are in Saturation. iD=1/2(1.5)^2 mA – Tony Stewart Sunnyskyguy EE75 Aug 14 '18 at 1:38
• But given the information in the problem how can you conclude that the voltage at the drain is 0V? – Connor T Desmond Aug 14 '18 at 1:49
• Because the V/I pairs are matched Req – Tony Stewart Sunnyskyguy EE75 Aug 14 '18 at 1:51
• What do you mean by V/I pair? I understand that both transistors will have the same RDS does this get closer to what you are getting at? – Connor T Desmond Aug 14 '18 at 2:04
• Thank you for your help. By creating treating each transistor as a resistor and using node-voltage to solve for the drain voltage it becomes apparent that the drain voltage is at 0V and thus both are in saturation. – Connor T Desmond Aug 14 '18 at 2:16

The issue here is that the output voltage is determined by the output impedance of both transistors. In the most simple model, the IV curves of the mosfets in saturation are completely flat.

This figure illustrates the issue (though I shifted the voltages with 2.5V, and ignore the currents as I just used a random model to make my point):

The blue lines are the drain currents of the NMOS for a number of different $V_{G}$ voltages. The green lines indicate the current through the PMOS for varying $V_{G}$ voltages - remember, $V_{out} = 5V - V_{SDp}$.

If you tie the gate voltages together, then as $V_{GSn}$ increases, $V_{GSp}$ will decrease. You select a blue and a green curve appropriately and find the intersection of the two curves to find the output current and voltage. You can read the output current on the Y-axis and the corresponding output voltage on the X-axis.

The most basic equations assume that the current is constant in saturation. This usually is not an issue, except for the single case where the horizontal lines match up. In other words, the intersection of the blue and green graph is not unique, but can be a whole range of points. And it is exactly in this situation that the exercise is biased. You will not find the output voltage using the "conventional" lowest level equations.

In order to solve it, you will have to account for the output impedance in saturation. This is the slope of the current when in saturation, and is typically modeled with the equation

$$i_{DS} = \frac{1}{2}k'\frac{W}{L}(V_{GS} - V_{T})^2(1 + \lambda V_{DS})$$