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I need some help selecting loading capacitors for a 32.768 kHz XTAL in a design I'm working on.

This is a bit long, but the big questions are: Is it critical to get the loading cap values right, and how important will the parasitic capacitance of the traces and leads be in determining this.

My device uses a TI CC1111 SoC, and is based on a reference design for a USB dongle available from TI. The CC1111 requires both a 48 MHz high-speed (HS) oscillator and a 32 kHz low-speed (LS) oscillator. The reference design uses a crystal for the HS oscillator, and an internal RC circuit for the LS oscillator. However, the CC11111 can be hooked up to a 32.768 kHz crystal oscillator for better accuracy, which I need.

The CC1111 datasheet provides a formula (p. 36) for choosing values for the loading capacitors. As a sanity check, I used that formula to calculate values for the caps used with the 48 MHz xtal in the reference design. I figured I should get roughly the same numbers that are actually used in the design. But the capacitance values I come up with don't match those used by TI, so I'm a bit concerned.

The details of my sleuthing are below, but in summary, the 48 MHz crystal's datasheet says it requires an 18pF load capacitance. The two load capacitors used in the reference design are both 22 pF. The CC1111 datasheet formula for relating the load capacitance seen across the leads of the xtal to the values for the load capacitors (\$C_a\$ and \$C_b\$) is

$$C_{load} = \frac{1}{\frac{1}{C_a} + \frac{1}{C_b}} + C_{parasitic}$$

Plugging in 18 pF for \$C_{load}\$ and 22 pF for \$C_a\$ and \$C_b\$, this means \$C_{parasitic}\$ must be 7 pF. However, the datasheet says this valus is typically 2.5 pF. If I had used this advice, I'd wind up with \$C_a\$ = \$C_b\$ = 31 pF, and not 22 pF as is actually used in the reference design.

Alternately, according to TI application note AN100,

$$C_{load} = \frac{C_1' \times C_2'}{C_1' + C_2'},$$

where "\$C_x'\$ is the sum of the capacitance in \$C_x\$, the parasitic capacitance in the PCB trace and the capacitance in the terminal of the crystal. The sum of the two latter parts will typically be in the range of 2 – 8 pF."

If \$C_1\$ = \$C_2\$ = 22 pF, you get \$C_1'\$ = 2*18 pF = 36 pF, so that the parasitic capacitance associated with each trace + terminal is 36pF - 22pF = 14 pF, which is outside of the 2 - 8 pF range cited in AN100.

I'm asking all this because I'm concerned that if I choose the wrong loading capacitor values, it either won't work, or the frequency will be wrong. How sensitive are these types of crystals to the loading cap values?

Details of my sleuthing:

From the Partlist.rep (BOM) included in the reference design zip file, the crystal (X2) and the two load capacitors to which it is connected (C203, C214) are:

X2   Crystal, ceramic SMD    4x2.5mX_48.000/20/35/20/18
C203 Capacitor 0402 C_22P_0402_NP0_J_50
C214 Capacitor 0402 C_22P_0402_NP0_J_50

So the load capacitors each have a value of 22 pF. The crystal, based on an answer to a previous TI E2E forum question for a related device, is this part:

Name: X_48.000/20/35/20/18
Descr.: Crystal, ceramic SMD, 4x2.5mm, +/-20ppm 48MHZ
Manf.: Abracon
Part #:  ABM8-48.000MHz-B2-T
Supplier: Mouser
Ordering Code: 815-ABM8-48-B2-T

The 18 pF value comes from the datasheet for the ABM8-48.000MHz-B2-T.

Thanks for your help.

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Most likely the 22pF values used by TI are a compromise (cost / availability). The crystal can generally tolerate a few pF plus or minus the calculated value. I would guess that some empirical testing went into the decision to use 22pF instead of a closer value, or perhaps 22pF was already on the BOM.

Ultimately, even a calculation like what's in the datasheet is based on stray capacitance 'guesstimation'. You have to test whatever capacitor value you come up with and make sure that it works in your end product.

Also, page 20 of the C1111 datasheet that you linked to says 12-18pF is the range to use for the 32.768kHz crystal. Your mileage may vary.

The most important thing to keep in mind is that the capacitor should be tight tolerance with an appropriate dielectric material (one that isn't highly temperature dependent, such as NP0/C0G).

Further reading: here's a link to a good explanation of the topic of how crystals and capacitors interact.

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  • \$\begingroup\$ Thanks. They datasheet recommends the Epson MC-306 32.768 kHz crystal, and I plan to order the 12.5 pF version. Thanks for the technical note, I'll read it. I've also since found this one, from TI: ti.com/lit/an/slaa322b/slaa322b.pdf. So if I'm not mistaken, I'll get my prototype PCB back from the fab house, see if it works, and if not, iterate? This sounds expensive. :^( \$\endgroup\$ – David Aug 31 '12 at 21:20
  • \$\begingroup\$ Another question: is +/- 2% OK? The datasheet recommends "Murata GRM1555C" series. I can find these in +/- 2% tolerances, but nobody seems to have the +/- 1% variety (i.e GRM1555C1E200FA01, where the 'F' is for 1% tolerance, and a 'G' would indicate 2% tolerance). \$\endgroup\$ – David Sep 4 '12 at 20:46
  • \$\begingroup\$ Anything better than 5% tolerance will be helpful. \$\endgroup\$ – Adam Lawrence Sep 4 '12 at 21:28
  • \$\begingroup\$ use NP0... or don't use NP0? \$\endgroup\$ – hassan789 Mar 17 '15 at 20:22
  • \$\begingroup\$ I wouldn't use NP0 in this application. \$\endgroup\$ – Adam Lawrence Mar 17 '15 at 20:23
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If you're trying to keep accurate time over a long period, you're probably going to need to calibrate the system somehow, as the 20ppm initial accuracy typically spec'd for these crystals will give you 15 minutes of error in a year before even looking at capacitors, crystal tempco (huge) and crystal drift. Some PIC processors have a calibration system that can compensate for a few hundred ppm of error, but you need to calibrate it at production or on-the-fly during use. Runtime temperature compensation of the crystal is critical if your system will operate more than a few degrees from 25ºC. In the big picture, capacitor stability is usually more important than initial tolerance.

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