My project has 9V and 3.3V on the board. I would like to use a precision voltage reference IC for the analog reference on the MCU (MCU powered by 3.3V).

The precision of the voltage reference IC is 0.5%, which is more precise than the 3.3V regulated output voltage from the regulator powering the MCU. The datasheet for the MCU says the AREF High voltage should never exceed the VDD.

In an ideal world, the voltage of the reference IC and the voltage from the switching regulator would both be exactly 3.3V. However, I am nervous of the real world possibility that the reference IC, with its high precision, will be a higher voltage that the VDD. For example, the reference IC could output 3.29V and the regulated voltage could end up being 3.22V. Is this enough to cause a problem? Or is this small of a difference negligible?

My alternative option would be to use a reference voltage of 3.0V and guarantee the reference voltage will ALWAYS be below the regulated 3.3V, However, it is easier to voltage clamp 3.3 volts as a ceiling for the analog inputs since I already have a 3.3V plane on the board.

Or would it be possible to use a 3V reference and still clamp to the 3.3V plane? According to the datasheet, the analog input voltage cannot exceed the reference voltage :( but IDK why...

Shouldn't the ADC value just max out at anything above the reference voltage? Obviously going above the 3.3V could cause damage...

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Any thoughts are appreciated!

  • \$\begingroup\$ It is always better to use an external Vref to avoid drift caused by the ADC/DAC/MPU warming up. An isolated Vref is much more stable. \$\endgroup\$ – VTNCaGNtdDVNalUy Aug 15 '18 at 1:54

There is usually a 0.2V margin for CMOS inputs outside the rails and a low current limit for Precision voltage references. But in your case only 0.1V for ADC input.


0.1% 20mA. 3.3V. $1 (1 pc)

Further protection could be done with enable output parts and low Vdd detect circuits, if you are unsure or check load current and add RC additional current limits/ filter to Vref to reduce to 5mA.

You could also consider 3.0V Vref regulator and Sch. Diode clamp to 3.3V. or better yet use a 16 bit ADC with an internal Vref.

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  • \$\begingroup\$ Thanks for the response! "There is usually a 0.2V margin for CMOS inputs outside the rails and a low current limit for Precision voltage references." I am not sure what the significance is of this...or was it just commenting on precision of the reference IC? \$\endgroup\$ – zme Aug 14 '18 at 23:39
  • \$\begingroup\$ CMOS ESD protection uses 5mA two stage 10kOhm Schottky diodes resulting in 0.2V drop from protection between inputs and rails \$\endgroup\$ – Tony Stewart Sunnyskyguy EE75 Aug 14 '18 at 23:42
  • \$\begingroup\$ I think I am going to go with the 3.0V reference IC and then still clamp the analog inputs to the 3.3V rail. I do not really expect the analog input to go above 3.0V, but the clamp is for fail-safe since the signal is coming from off the board... Thank you so much for your time. I appreciate it! \$\endgroup\$ – zme Aug 15 '18 at 0:03
  • \$\begingroup\$ There will be tolerance to clamping, because the ESD structures/diodes will be sloppy in their trigger points. \$\endgroup\$ – analogsystemsrf Aug 15 '18 at 3:33

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