I was studying a schematic of an universal 48-pin device programmer, and while most of it seems pretty straightforward to me, I have trouble understanding the reasons behind some of the decisions made by the original author for the pin driver circuit. Below is the block diagram of the programmer:

block diagram

Combined schematic for a single pin looks like this:


simulate this circuit – Schematic created using CircuitLab

Each of the 48 pins can be connected to GND, VCCX (a programmable voltage VCC rail), VPP (a programmable voltage VPP rail), or act as an input pin. The questions I am asking for help with are (please refer to full schematic linked above):

  1. Why use an ULN2003L to control base of QVPP to switch the VPP voltage for a pin? Why not drive the base directly from the output of SN74LVTH273DW?
  2. What is the function of schottky diode in VCCX switch?
  3. Each pin is connected to a FPGA via two resistors and a diode (BAV70), see the block diagram. How is the FPGA being protected from high voltage (e.g. 5 volts) potentially being output by programmed chip to some of its pins?
  4. All pins are also connected to a common PULLUP (which can be switched to be either pull-up or pull-down by the MCU), but I don't get why would one need to pull all pins at once to VCCX or GND, and why wouldn't doing so interfere with supplying power to the chip's power supply pins? Or, perhaps the PULLUP function is there for a self-test to change state of all pins and read them back in FPGA?

Thanks in advance!


1 Answer 1

  1. The drive signal has to rise approximately to Vpp to turn that transistor off. That is not possible with direct drive and Vpp greater than the supply of the 74HC chip. Something with an open collector or open drain fills the bill, and the ULN2003 is cheap and has 7 such outputs.

  2. If the pin is switched to Vpp > Vcc the transistor would otherwise conduct, even with base drive = Vccx (off). There is a bit of variable voltage drop (depending on current) due to the diode so it's not ideal, but it's a cheaper solution than using a better switch design.

  3. The diode and series resistor clamps the voltage to Vcc plus a diode drop and the additional series resistor keeps the current into the FPGA input protection network relatively low. It's a cheap solution that is probably adequate in many situations.

  4. Probably just to deal with inputs on the target device that may be outputs from time to time, and should be held in some defined state when inputs. It would be better to have the pins individually programmed as high-Z, pull-up, or pull-down but this arrangement is cheaper/simpler and adequate for most situations.

  • \$\begingroup\$ Thanks for a detailed explanation! Now I am also curious what will an equivalent circuit look like if BJTs are replaced with logic-level MOSFETs and if it will simplify it or make it more complicated? \$\endgroup\$ Aug 15, 2018 at 11:21
  • \$\begingroup\$ It would be quite similar if the design was similar (ie. not improved). More resistors (though there arguably should be B-E resistors on the BJTs as well). The P-channel MOSFETs would have to handle Vgs = Vpp or there would need to be zeners etc. You would still need the Schottky diodes in your Q2 because of the body diode of the MOSFET. \$\endgroup\$ Aug 15, 2018 at 11:45

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