Standard SPI uses single-ended signals. Is it possible that a communication uses SPI protocol but the signals are physically LVDS?

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    \$\begingroup\$ Yes. But you need to make the question more specific. \$\endgroup\$
    – Jeroen3
    Aug 16 '18 at 5:26
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    \$\begingroup\$ I have done it to run SPI over longer distances. You can run into problems with signal timing due to all the gate delays. \$\endgroup\$
    – mkeith
    Aug 16 '18 at 5:54
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    \$\begingroup\$ It is possible, in principal, as long as your timing margin is not consumed by propagation delay. MISO cannot transition until after the applicable clock edge is received at the slave. So the clock needs to be converted from single-ended to differential, then back to SE, then slave asserts new data on MISO, then MISO is converted from SE to differential and back to SE at the master. Your timing budget can get consumed by all those transitions. You just need to keep an eye on it. \$\endgroup\$
    – mkeith
    Aug 16 '18 at 6:32
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    \$\begingroup\$ See Application note slyt441 \$\endgroup\$
    – Jeroen3
    Aug 16 '18 at 7:11
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    \$\begingroup\$ @Oldfart In that app note that's the SCLK which is generated by master. it makes a round trip to the slave and back to the master. The controller uses one SPI peripheral as a master for sending the data (it generates the SCLK) and another SPI peripheral as a slave for receiving the data. The receiving happens kind of asynchronously with respect to transmitting, because of the length of the cable. Having said that, I don't think that app note actually applies to the O.P. situation. 1m is short w.r.t. 1MHz . \$\endgroup\$ Sep 29 '19 at 3:18


Typical reason for doing this is to extend a relatively fast(for SPI! -- only 30 to 100 MHz) SPI bus over a cable between PCBs without running into EMI problems -- both excessive emission and interference -- possibly with other such busses or pcbs within the same (hopefully well shielded) box.

SPI is really intended to be used on a single PCB, preferably with a ground plane to make the traces into poor antennae.

But nowadays there are a lot of 'pcb modules' which I have seen require up to 80 MHz SPI to fully utilize ... through 0.1" headers. These tend to be quite noisy if operated at full speed. So it becomes desirable to do something about that noise.

One can 'retrofit' LVDS to existing single-ended SPI circuit board modules using a single-pair LVDS transmitter chips like the DS90LV011A. Its possible then to put those little chips on individual soic to 0.1" header boards, and just wire wrap them up to the headers on the slave PCB.

But it's considerably cheaper to not bother with the receiver chips at the slave module -- just terminate the complement signals to a resistor to ground on that board, and tweak the resistance until the return current settles down. (Still generate and 'send' the complement signals to the slave board! The presence of their current in the wires nearby the non-complement signals is what cancels the EMI).

The reason this works is because LVDS attempts to force both each logic line and its complement to carry a total current that together looks as constant as possible, regardless of logic transitions.

It's possible to twist wire-wrap or hookup wire together and use one twisted pair per signal pair. This is not done for (good) impedance matching, rather it tends to further reduce EMI because the current ends up taking largely the same spatial path on average regardless of which logic state its in. (This is also largely how USB2 gets away with such simple wiring).

The electromagnetic emission depends on the total return current loop area and the rate of change of the current in the wire around that loop. Using LVDS, there are two loops, whose area(s) overlaps almost perfectly, so that a logic state change doesn't result in a change of current around said area.

Usually such links don't bother meeting the full spec requirements for impedance matching. (for example, using a parallel cable rather than something like a SATA cable, which has independent coax for each half of each pair, and will consequently go much faster).

This can be fudged because there is more time at typical SPI clock rates to allow overshoot etc to settle down -- one just uses source series termination with tweaked resistor values to keep the reflection down.

LVDS is also 'abused' this way for things like shaft encoder signals. (eg, some of Kistler's). But again, this is because of LVDS's good interference rejection, not because the encoder needs to handle billions of edges per second (they don't!). The cable length reduces the max frequency that LVDS can attain, because of the greater cable capacitance.

All of the above use LVDS at much lower data rates than one would typically choose it for, because it does a better job at both interference rejection and suppression than single ended logic does. (and may be more convenient or still faster than a larger-swing standard like RS-422).

One can still achieve very high rates between boards using it over hookup or wire-wrap wires, but it becomes somewhat of a pain to wire up because one has to achieve a good impedance match for each signal and its complement independently (a pair of twisted pairs), whilst keeping both the same length.

This is so much easier to do with a cable designed for the job, such as SATA cables. (which are designed to carry just two LVDS pairs, one for transmit, and one for receive, both using an encoding which carries both the clock and data, such as 8b/10b. There are four tiny coax cables because what one really has is two independent single-ended transmission lines... which happen to be close to each other, but note they have separate screening).

But by the time you've got four tiny coax lines, you could just use single-ended SPI directly over such a cable anyway, since the coax restricts the 'loop area' to live entirely enclosed in the 100% screen they have.

At high speed also, one needs to deal with the phase lag introduced by the speed of the electrical impulses (usually about .6 c or so). For an SPI bus, this means receiving the noticeably-late MISO signal with a different, deliberately delayed clock.

It's usually best to use another pair alongside the MISO lines to carry the same clock over the same distance as the return from the MISO has to follow back to the master, but you have to be able to use it. FPGAs easily do this, but I have yet to see a built-in 'SPI master' interface on a micro-controller which can.

This amounts to having a separate 'receive-only SPI slave interface' that can run concurrently alongside one's 'transmit-only SPI master', that both just so happen to use almost the same packet timing.

If one were to use an actual separate slave SPI interface, one would also have to copy-back the CS at the cost of yet another pair, at which point you could probably buy an FPGA for less than the cost of the required LVDS chips.

An additional option that's available on many FPGA's is the ability to internally generate a second derived clock with an adjusted phase delay, so as to match the clock one would have received from the 'returned' clock so as to allow for proper reception of MISO without having to 'send the clock back'.


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