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I wanted to understand, if MIPI CSI-2(LVDS-like) should result in a larger power consumption than the traditional signle-ended digital parallel interface. The MIPI is widely used today, but the parallel interface is also used for low resolution image sensors. So if one should use a sensor that supports both MIPI CSI or parallel interface, then the person must choose one. In terms of performance, MIPI would be better, due to its lower noise and EMI. However, is it normal to expect that using the MIPI would result in a larger power consumption?

Let's say one controls an image sensor using an FPGA and a SDRAM. The frequency of the parallel signal is 50Mhz, and the bitwidth is 8-bits, while the frequency of the MIPI CSI-2 is 200Mhz, and it uses two lanes. Also let's assume the SDRAM clock frequency is 133Mhz, which means the FPGA should be fast enough to handle the SDRAM as well.

Thinking about the dynamic power consumption of the CMOS I/Os, the parallel transmission seems to consume less power, because 50Mhz x 8 lines < 200Mhz x 4 lines. Also clocking FPGA to cover 200Mhz signals would increase the power consumption of the FPGA even further. Does this reasoning make sense?

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  • \$\begingroup\$ 50M for parallel video is a little challenging. \$\endgroup\$ – user3528438 Aug 16 '18 at 7:37
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It's just the data bus used. The data processing on either side is the same, irrespective of the bus. I'd expect that to dominate power consumption.

While driving many LVDS lines certainly costs energy, I doubt that the difference to a single-ended interface of the same voltage difference is significant. On the contrary: on a single-ended line, you'd typically need a stronger driver, hence more power. But that's just a rule of thumb.

Now, it's clear that this is very much chip-specific. So, if the manufacturer or its datasheet don't tell you, build both and measure.

Or go with the MIPI interface. It's been designed for low-power applications.

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