I was reading an old schematic and found this and sketched it up; (see box in image "Some kind of protection")

Some kind of protection The closest thing to this schematic that I've been able to find, that could have briefly explained how it was works used a depletion mode NMOS to act as an over voltage protection circuit. Over voltage protection with depletion mode NMOS

That could have explained it! Sadly the NMOS used is a IRFBG20 that isn't a depletion mode fet, if I did not now totally misread..

So I wonder, is there something I've missed? This design is in use, so it should work somehow..


That's input overvoltage protection. Essentially it's a voltage regulator. The 3 zeners produce about 810 volts (nominally), so at nominal 700 volts in the gate of the FET is at 700 volts. Then the FET will produce a source voltage of about 10 volts less, or on the order of 690 volts, since a 10-12 volt Vgs should turn it on fully.

If the input voltage ever gets above about 810 volts (+/- whatever the zener tolerances are) the gate voltage will be clamped at 810 (+/-) so the output will also be clamped.

ETA - As the input rises, so does the gate voltage. If (for instance) Vgs of 10 volts is enough to fully turn on the FET, then as the input rises above 10 volts the FET will be turned on and charge C1, with R3 taking up the slack. Once the input reaches its peak, if there is no current drain through the transformer, the output will gradually rise the final 10 volts or so until the FET is turned off. However, in operation the capacitor voltage will vary, and this will turn on the FET to produce the necessary current.

For instance, let's say the cap is 10 uF and the turn-on time of the input is 7 msec, for an input dV/dt of 100 V/msec. Then the turn-on current will be 1 amp, which is well within capability. If the cap were 1000 uF, it would need 100 amps, which the FET cannot provide. However, the 100 ohm R3 means that, in the worst case, the charge current would be 7 amps (700 V/ 100 ohms), so that should not be a problem.

It may help to visualize the transformer circuit as a simple resistor to ground, with a value which produces an appropriate average current level. You can do this due to the lowpass action of R3/C1, which will buffer the current spikes actually produced. Then the average cap voltage will stabilize, with the cap voltage plus the iR drop on R3 adding up to just enough less than the input voltage to keep the FET operating correctly. If Vgs is too low, the FET will not be properly turned on, the voltage across R3 will be less, and the FET will turn on more. Vice versa if the FET is on too hard, although this obviously has no potential to hurt the FET.

| improve this answer | |
  • \$\begingroup\$ I can't see how that practically can work. At the start I would say that the gate is charged to Vth, then the FET opens, but then the source voltage will be almost as high as the drain so the FET will turn off. So how is the Vgs kept over Vth and in the safe region of Vgs? \$\endgroup\$ – Anton Ingemarson Aug 16 '18 at 13:06
  • \$\begingroup\$ @AntonIngemarson - See edit. The voltage on the cap and iR drop on R3 cause the circuit to possess negative feedback, and it will self-regulate. \$\endgroup\$ – WhatRoughBeast Aug 16 '18 at 16:50

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.