This is related to this question: How's my crystal oscillator layout?

I'm trying to layout a 12MHz crystal for a micro controller. I've been reading through several recommendations specifically for crystals as well as for high frequency design.

For the most part they seem to agree on a few things:

  1. Keep traces as short as possible.
  2. Keep differential trace pairs as close to the same length as possible.
  3. Isolate the crystal from anything else.
  4. Use ground planes beneath the crystal.
  5. Avoid vias for signal lines.
  6. Avoid right angle bends on traces

Here's the layout of what I currently have for my crystal:

crystal layout

The red represents the top PCB copper and blue is the bottom PCB layer (it's a 2-layer design). The grid is 0.25mm. There's a complete ground plane beneath the crystal (blue layer), and surrounding the crystal is a ground tied to the bottom ground plane using several vias. The trace connecting to the pin next to the clock pins is for the uC's external reset. It should be held at ~5V, and a reset is triggered when it's shorted to ground.

There are still a few questions I had:

  1. I've seen a few recommended layouts which place the load capacitors closer to the IC and others which place them on the far side. What differences can I expect between the two, and which one is recommended (if any)?
  2. Should I remove the ground plane from directly beneath signal traces? It seems like that would be the best way to reduce the parasitic capacitance on the signal lines.
  3. Would you recommend thicker or thinner traces? Currently I have 10mil traces.
  4. When should I bring the two clock signals together? I've seen recommendations where the two lines are directed essentially towards each other before heading to the uC, and other where they are kept apart and brought slowly together like I currently have.

Is this a good layout? How could it be improved?

Sources I've read through so far (hopefully this covers most of them, I might be missing a few):

  1. TI's recommendations for high speed layout guidelines
  2. Atmel's AVR hardware design considerations
  3. Atmel's Best Practices for the PCB layout of oscillators


Thanks for your suggestions. I've made the following changes to my layout:

  1. The bottom layer beneath the uC is being used as a 5V power plane and the top layer is a local ground plane. The ground plane has a single via to the global ground plane (bottom layer) where the 5V joins together to the source, and there's a 4.7uF ceramic capacitor between the two. Made routing ground and power much easier!
  2. I've removed the top ground elements directly under the crystal to prevent shorting out the crystal casing.
  3. @RussellMcMahon, I'm not sure what exactly you mean by minimize the loop area. I've uploaded a revised layout where I bring the crystal leads together before sending them to the uC. Is this what you meant?
  4. I'm not entirely sure how I can complete my guard ring loop around the crystal (right now it's kind of a hook-shape). Should I run two vias to connect the ends (isolated from the global ground), remove the partial-ring, or just leave it as it is?
  5. Should I remove the global ground from beneath the crystal/cap?

updated layout

  • \$\begingroup\$ this is good, you will not have a problem at 12MHz. It is slow. Place caps close to the crystal. For this frequency no gnd is needed. Thickness is not in play, they will not carry any current. \$\endgroup\$
    – Ktc
    Commented Aug 30, 2012 at 11:15
  • \$\begingroup\$ Looks good enough. Xtal as close to IC as reasonably possible. | Minimise loop area of conducting loop. eg here bring leads further out before turning under xtal. Few people do that. Consider in extreme cases turning xtal at 90 degrees to reduce loop area to almost zero. | Watch extent of insulation around pins compared to top pad size. Be sure not to short can to pads (has been known to happen.) \$\endgroup\$
    – Russell McMahon
    Commented Aug 30, 2012 at 16:54
  • \$\begingroup\$ @RussellMcMahon I'm not entirely sure if I understood you correctly about minimizing the loop area. I uploaded a new layout where the crystal leads go directly to each other before heading to the uC. Is this what you meant? \$\endgroup\$ Commented Aug 30, 2012 at 17:34
  • \$\begingroup\$ Keep the XTALIN and XTALOUT as far away from each other as possible to reduce capacitive coupling between the signals and add a ground between them. The Miller effect amplifies the cross capacitance and can even kill the oscillations. \$\endgroup\$
    – PkP
    Commented Aug 15, 2016 at 19:41

2 Answers 2


Your placement is fine.

Your routing of the crystal signal traces is fine.

Your grounding is bad. Fortunately, doing it better actually makes your PCB design easier. There will be significant high frequency content in the microcontroller return currents and the currents thru the crystal caps. These should be contained locally and NOT allowed to flow accross the main ground plane. If you don't avoid that, you don't have a ground plane anymore but a center-fed patch antenna.

Tie all the ground immediately associated with the micro together on the top layer. This includes the micro's ground pins and the ground side of the crystal caps. Then connect this net to the main ground plane in only one place. This way the high frequency loop currents caused by the micro and the crystal stay on the local net. The only current flowing thru the connection to the main ground plane are the return currents seen by the rest of the circuit.

For extra credit, so something similar with the micro's power net, place the two single feed points near each other, then put a 10 µF or so ceramic cap right between the two immediately on the micro side of the feed points. The cap becomes a second level shunt for high frequency power to ground currents produced by the micro circuit, and the closeness of the feed points reduces the patch antenna drive level of whatever escapes your other defenses.

For more details, see https://electronics.stackexchange.com/a/15143/4512.

Added in response to your new layout:

This is definitely better in that the high frequency loop currents are kept of the main ground plane. That should reduce overall radiation from the board. Since all antennas work symmetrically as receivers and transmitters, that also reduces your susceptibility to external signals.

I don't see the need to make the ground trace from the crystal caps back to the micro so fat. There is little harm in it, but it is not necessary. The currents are quite small, so even just a 8 mil trace will be fine.

I really don't see the point to the deliberate antenna coming down from the crystal caps and wrapping around the crystal. Your signals are well below where that will start to resonate, but adding gratuitous antennas when no RF transmission or reception is intended is not a good idea. You apparently are trying to put a "guard ring" around the crystal, but gave no justification why. Unless you have very high nearby dV/dt and poorly made crystals, there is no reason they need to have guard rings.

  • 5
    \$\begingroup\$ OP has made some edits to the question after your suggestion. And I am very curious about your thoughts on the layout after the edit :) \$\endgroup\$ Commented Aug 30, 2012 at 17:53
  • 3
    \$\begingroup\$ That is an interesting point about the guard ring. In my last design, I implemented such a guard ring, as it was recommended in an Atmel appnote. ( atmel.com/images/doc2521.pdf ) I had no issues with my clocking, but then again I did not get it FCC approved either. \$\endgroup\$
    – dext0rb
    Commented Aug 30, 2012 at 20:51
  • 4
    \$\begingroup\$ @abdullah: It means it doesn't do any harm, but doesn't provide much benefit either. In other words, there is no need to bother doing that, but not going to hurt anything if you do. \$\endgroup\$ Commented Aug 31, 2012 at 13:00
  • 7
    \$\begingroup\$ @abdullah: Yes, wider traces have less inductance and less resistance. However, the difference is so small in a case like this where the crystal is close to its driver that it is immeterial. I routinely use 8 mil traces and haven't observed any problems. Wider traces take more space and have more capacitance to elsewhere. \$\endgroup\$ Commented Sep 1, 2012 at 12:40
  • 6
    \$\begingroup\$ "you don't have a ground plane anymore but a center-fed patch antenna" - probably the most punch-per-sentence I've read all week :) Couldn't agree more. \$\endgroup\$ Commented Jan 23, 2015 at 19:07

Take a look at Atmel's application note AVR186, "Best Practices for the PCB layout of Oscillators" at http://ww1.microchip.com/downloads/en/DeviceDoc/Atmel-8128-Best-Practices-for-the-PCB-Layout-of-Oscillators_ApplicationNote_AVR186.pdf

Place the load caps next to the IC; between the IC and the crystal. Keep the XTALI, XTALO traces short but minimize their capacitive coupling by keeping the traces as far away from each other as possible. If you need to make the traces longer than half an inch, put a ground wire between them to kill the cross capacitance. Surround the traces with ground on all sides and put a ground plane under the whole thing.

Keep the traces short.


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