This is related to this question: How's my crystal oscillator layout?
I'm trying to layout a 12MHz crystal for a micro controller. I've been reading through several recommendations specifically for crystals as well as for high frequency design.
For the most part they seem to agree on a few things:
- Keep traces as short as possible.
- Keep differential trace pairs as close to the same length as possible.
- Isolate the crystal from anything else.
- Use ground planes beneath the crystal.
- Avoid vias for signal lines.
- Avoid right angle bends on traces
Here's the layout of what I currently have for my crystal:
The red represents the top PCB copper and blue is the bottom PCB layer (it's a 2-layer design). The grid is 0.25mm. There's a complete ground plane beneath the crystal (blue layer), and surrounding the crystal is a ground tied to the bottom ground plane using several vias. The trace connecting to the pin next to the clock pins is for the uC's external reset. It should be held at ~5V, and a reset is triggered when it's shorted to ground.
There are still a few questions I had:
- I've seen a few recommended layouts which place the load capacitors closer to the IC and others which place them on the far side. What differences can I expect between the two, and which one is recommended (if any)?
- Should I remove the ground plane from directly beneath signal traces? It seems like that would be the best way to reduce the parasitic capacitance on the signal lines.
- Would you recommend thicker or thinner traces? Currently I have 10mil traces.
- When should I bring the two clock signals together? I've seen recommendations where the two lines are directed essentially towards each other before heading to the uC, and other where they are kept apart and brought slowly together like I currently have.
Is this a good layout? How could it be improved?
Sources I've read through so far (hopefully this covers most of them, I might be missing a few):
- TI's recommendations for high speed layout guidelines
- Atmel's AVR hardware design considerations
- Atmel's Best Practices for the PCB layout of oscillators
Thanks for your suggestions. I've made the following changes to my layout:
- The bottom layer beneath the uC is being used as a 5V power plane and the top layer is a local ground plane. The ground plane has a single via to the global ground plane (bottom layer) where the 5V joins together to the source, and there's a 4.7uF ceramic capacitor between the two. Made routing ground and power much easier!
- I've removed the top ground elements directly under the crystal to prevent shorting out the crystal casing.
- @RussellMcMahon, I'm not sure what exactly you mean by minimize the loop area. I've uploaded a revised layout where I bring the crystal leads together before sending them to the uC. Is this what you meant?
- I'm not entirely sure how I can complete my guard ring loop around the crystal (right now it's kind of a hook-shape). Should I run two vias to connect the ends (isolated from the global ground), remove the partial-ring, or just leave it as it is?
- Should I remove the global ground from beneath the crystal/cap?