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Question: What is the electrical advantage to paralleling smaller capacitors to reach a given capacitance, rather than using fewer smaller capacitors on the output of a DC power supply?

For example, using 10x10uF, instead of 1x100uF, 2x47uF, 3x33 uF...

I think it may be to lower overall ESR (see 1st point in 1st answer here). If that's all it is, fair enough, question closed.

The question comes from TI's webench tool; the few design requirements I've inputted spit out schematics like below, with 9x22uF caps instead of 2x100uF or similar. Note: the schematic combines a few output caps, but I've attached a grab of the BOM also to show its 9.

I'm not sure if they do this to optimize another side of the design; PCB space, cost, etc. The tool lets you optimize your design by cost, PCB space, and efficiency.

Schematic: Schematic

Bill of Materials: BOM

Optimization Dial: Optimization Dial

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  • \$\begingroup\$ Smaller caps will resonate at higher frequencies, and the Rdampen will need to increase, by the sqrt( L / C). \$\endgroup\$ – analogsystemsrf Aug 17 '18 at 4:09
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Smaller size capacitors have lower ESL. Paralleling many of them lowers ESR and ESL further. This can lower noise on the output of a switching regulator, but very low ESR can also create a high Q resonance when interacting with other capacitors on the power bus. When comparing 10X 10uF to 1X 100uF you have to consider if they are the same type of capacitor or not. For instance 10uF might be ceramic and 100uF might be tantalum or electrolytic. Ceramic capacitors loose capacity proportional to DC bias voltage, this is worse for smaller size packages. 10X 10uF ceramic may only give you 50uF. Ceramic capacitors are also limited in capacitance so if you need 100uF or more, chances are you need to parallel them.

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