I have a Cyclone V GX starter kit. It comes with 4884 bits on-chip memory. I want to write a module for accessing the on-chip memory. So, I have generated the RAM IP reference design from the IP catalog like this:
module onchipmem ( aclr, address, clken, clock, data, rden, wren, q); input aclr; input [7:0] address; input clken; input clock; input [15:0] data; input rden; input wren; output [15:0] q; `ifndef ALTERA_RESERVED_QIS // synopsys translate_off `endif tri0 aclr; tri1 clken; tri1 clock; tri1 rden; `ifndef ALTERA_RESERVED_QIS // synopsys translate_on `endif wire [15:0] sub_wire0; wire [15:0] q = sub_wire0[15:0]; altsyncram altsyncram_component ( ... );
I can write / read data by creating an instance of this module:
onchipmem write_mem ( .aclr(reset), .address(address), .clken(ce), .clock(clk), .data(data), .rden(1'b0), .wren(1'b1), .q() );
I want to save data by
onchipmem in one module and read data from the same instance of
onchipmem from another module. However, creating multiple instances of
onchipmem will allocate duplicated block of RAM per instance.
In other words, a single RAM module cannot be called by multiple modules. So how to implement a share RAM module for multiple modules to access?
I found this answer that suggested using an
arbiter. He provided some sample codes of an arbiter but it is not completed.
I am new to FPGA and cannot get how it works.
So I am looking for a real and completed example so that I can learn and test it in ModelSim.