# BJT: Equation of Vce for Saturation Region

In Sedra and Smith: Microelectronics Circuits (6E), it is mentioned, on page 185:

Recalling that the CBJ is much larger than the EBJ, the forward-voltage drop $v_{BC}$ will be smaller than $v_{BE}$ resulting in a collector-emitter voltage, $v_{CE}$, of 0.1 V to 0.3 V.

Why does a difference in junction area causes a change in the forward-voltage drop? A similar question was asked on the site, however, it did not help.

So, I tried using Ebers-Moll model and that is where I am actually getting stuck. So, my question is this:

How should I apply Ebers-Moll method for a transistor working in a saturation region, to get the equation for $V_{ce}$?

So far, I know that there are three major Ebers-Moll models, here. I also read that the $I_{s}$ is a property of the emitter-base junction.
Additionally, $i_{c} \leq \beta i_{b}$.

There is no formula for Vce(sat) because this bulk resistance is process dependent. The chip size, doping, layered etching methods all are factors.

You must refer to the Vce(sat) parametric model or datasheet for this property.

Diodes Inc (nee Zetex) has many of the earliest process patents of ultra-low Vce(sat) at high currents. They were also the first to characterize this as Rce, a linear resistance, in datasheets.

This collector-emitter saturation bulk resistance called $$\R_{CE}\$$ is defined for Vce=Vce(sat) at Ic/Ib=10 at various currents. In some cases, the log-log, or linear graph of Ic vs Vce shows the linear property above 10% of Imax.

example of Rce p.2 of 5 SOT-23
Prior to Zetex, you had to get a big power transistor in TO-3 can to get this low value of ~Vce(sat)/Ic.

Equivalent On-Resistance Rce(SAT) 35m typ 50 mΩ max. @Ie = 2A, Ib = 200mA

I have often referred to bulk resistance in diodes as ESR and this property is always inversely related to package power rating ( and thus chip size) as a designer's figure of merit (FoM). This property exists for all diodes and LEDs.

• Also Ic approaches 10%β*ib at Vce(sat), so that ultra-low Vce(sat) parts tend to have extremely high β.
• Isn't $\beta$ = Ic/Ib, so why would low Vce(sat) have high $\beta$? As I am given to understand, the lower Vce(sat) the more deep-saturated the transistor gets, consequently reducing the collector current. So shouldn't $\beta$ be smaller? Aug 19, 2018 at 6:42

Why does a difference in junction area causes a change in the forward-voltage drop?

Consider the shockley diode equation: -

If a diode has a higher reverse saturation current ($I_S$) then, for a given forward volt drop ($V_D$) across it, there is more forward current ($I_D$). Alternatively, for a given (and constrained) forward current there is a smaller forward volt drop compared to a diode having a lower reverse saturation current.

In heavy saturation the BC junction is starting to forward conduct and, because it has a bigger surface area compared to the BE junction it naturally has a higher reverse saturation current therefore, it has a lower volt drop from base to collector compared to base/emitter.

In other words the collector can never fully get down to the emitter voltage when the transistor is saturated because it is being "held up" (or supported by) the base voltage.

• +1, thank you for explaining the text. But my question was, 'how do I derive the equation for $V_{CE}$ in saturation using the Ebers-Moll model?' Aug 18, 2018 at 19:33
• @MohammedArshaan Ebers Moll does not work very well when the transistor is in saturation so it's probably not worth persuing that line of enquiry. Here is a pdf from Imperial college explaining how SPICE simulations overcome this problem and note what it says on page 2 - The exponential equation is not accurate in the saturation region Aug 18, 2018 at 19:46
• Ok, I understand but is there any way to derive the equations for a BJT in saturation? Aug 19, 2018 at 6:46
• I'm not that sufficiently up on the physics to make a good hand at that. You are bordering physics territory so maybe ask that specific question on the physics site. Aug 19, 2018 at 9:49