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In FPGA world, what exactly are false path constraints for an HDL compiler? Why are they useful?

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    \$\begingroup\$ This is a digital concept, not just a FPGA concept. \$\endgroup\$ – W5VO Aug 31 '12 at 3:31
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False paths are timing paths that will never really be exercised in the final design. Suppose you are designing a 4-bit counter and it turns out that there is a very slow delay path when incrementing from 12 to 13. If your design always resets the counter whenever the count equals 9 then that slow path will never be seen in the actual design. You label the slow path as a false path so that the compiler doesn't spend any time, or add any extra logic, in an effort to make the false path run faster.

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    \$\begingroup\$ Huh, and I thought false path had to do with using Atmels instead of PICs or something. \$\endgroup\$ – Olin Lathrop Aug 30 '12 at 20:58
  • \$\begingroup\$ A more significant type of false path I think is a signal which changes on the edge of one clock and is sampled on the edge of a different clock, but either the signal will never actually change anywhere near the time the second clock changes, or if it does change nothing will care about its value. Timing analysis tools would likely fail unless one added a double synchronizer which was controlled by the second clock, but adding such a synchronizer might totally break the design. For example, the first clock might run at 1MHz and the second at 32KHz, but... \$\endgroup\$ – supercat Aug 31 '12 at 14:54
  • \$\begingroup\$ ...the device generating the signal might change it three 1MHz cycles after it sees a rising edge on the 32KHz clock. Consequently, the signal latched by the 32kHz clock might be guaranteed to comply with the sample/hold requirements of the 32kHz latch without any extra synchronization. If the logic on the 1MHz side generated its data based upon what the 32KHz side was doing, such a design could allow information generated on one cycle on the 32Khz side to percolate both ways by the next cycle. Adding double synchronization to the 32Khz side would break that. \$\endgroup\$ – supercat Aug 31 '12 at 14:58
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A false path is a path that does exist in the design but does not play a part in the operation, so it's not necessary to include it in the timing analysis.
There could be various reasons for this being the case, but since the timing analysis tool usually doesn't know (although there are some tools which can detect them) which paths may be used or not, you have to tell it. It's similar to a multi-cycle path, where you can tell it that a certain path is allowed to use more than one cycle to complete.

An example (of a false path) is a register that might be written once on power up, but then remains in the same state.

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Simply, a false path is a logic path that you want excluded from being checked to see if it meets timing during timing analysis. There are two of reasons to exclude paths, first because the false path will make the tools work harder to meet timing for that signal which will in turn affect legitimate signal paths possibly causing additional timing errors and because it will cause the timing check to report failures possibly distracting the designer from legitimate timing errors.

False paths are caused by logic paths between unrelated asynchronous clocks or clocks of the same frequency but with unknown phase relationship or a path that would never be activated during normal circuit operation. Telling the tool to ignore a path doesn't make the timing work only that the timing is not checked. It is up to the designer to manually insure the correct synchronizing logic is used for these ignored signal paths.

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