In FPGA world, what exactly are false path constraints for an HDL compiler? Why are they useful?
False paths are timing paths that will never really be exercised in the final design. Suppose you are designing a 4-bit counter and it turns out that there is a very slow delay path when incrementing from 12 to 13. If your design always resets the counter whenever the count equals 9 then that slow path will never be seen in the actual design. You label the slow path as a false path so that the compiler doesn't spend any time, or add any extra logic, in an effort to make the false path run faster.
A false path is a path that does exist in the design but does not play a part in the operation, so it's not necessary to include it in the timing analysis.
There could be various reasons for this being the case, but since the timing analysis tool usually doesn't know (although there are some tools which can detect them) which paths may be used or not, you have to tell it. It's similar to a multi-cycle path, where you can tell it that a certain path is allowed to use more than one cycle to complete.
An example (of a false path) is a register that might be written once on power up, but then remains in the same state.
Simply, a false path is a logic path that you want excluded from being checked to see if it meets timing during timing analysis. There are two of reasons to exclude paths, first because the false path will make the tools work harder to meet timing for that signal which will in turn affect legitimate signal paths possibly causing additional timing errors and because it will cause the timing check to report failures possibly distracting the designer from legitimate timing errors.
False paths are caused by logic paths between unrelated asynchronous clocks or clocks of the same frequency but with unknown phase relationship or a path that would never be activated during normal circuit operation. Telling the tool to ignore a path doesn't make the timing work only that the timing is not checked. It is up to the designer to manually insure the correct synchronizing logic is used for these ignored signal paths.