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let me know what I state below is correct or not.

Regarding the DNL and INL of a DAC, DNL is the error difference between actual step width and ideal value (1 LSB). INL is the deviation of actual transfer function from the shown straight line (Shown in image below).

My understanding is, that to guarantee no missing codes and a monotonic transfer function, the DNL must be less than 1 LSB.

Regarding my DAC ICs, the DAC IC #1 I found has a INL of +/- 0.4 and DNL of +/- 0.1. Now, the previous DAC IC #2 had a DNL value of +/- 1 and INL value of +/- 4. All the other specs regarding these two different DACs are the same.

Do you think this is a very crucial thing to consider in choosing a DAC IC and did I make the right decision by looking and choosing DAC IC #1 over the previous DAC IC #2?

Notes

Essentially, this DAC takes in a SDA and SCL I2C signal. It also takes in a 7-bit address selection.

The output signal is DC.

  • Data Interface: 400 KHz I2C interface.
  • 27 selectable addresses
  • Number of Bits: 14
  • Number of D/A Converters: 1
  • Settling TIme: 9 uS
  • Output Type: Voltage - Buffered
  • No Differential Output
  • Voltage - Supply, Analog - 2.7 V ~ 5.5 V
  • Voltage - Supply, Digital - 2.7V ~ 5.5 V

INL AND DNL

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  • \$\begingroup\$ INL and DNL are very dependent on the application. Some applications can't tolerate one or the other. Please edit your question and describe the application, and if the output is DC or AC or if there is any signal generation and how fast the update rate is. \$\endgroup\$ – Voltage Spike Aug 20 '18 at 16:46
  • \$\begingroup\$ @laptop2d Is that sufficient information for you? Let me know, I edited the questions. Thank You. \$\endgroup\$ – tnet Aug 20 '18 at 16:54
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    \$\begingroup\$ Without a list of requirements for your target design nobody but you can tell if either DAC is suitable or not. \$\endgroup\$ – Andy aka Aug 20 '18 at 19:19
  • \$\begingroup\$ Could your system still behave properly, if the DAC had 13 bits? or 12 bits? or 11 bits? \$\endgroup\$ – analogsystemsrf Aug 21 '18 at 3:31
  • \$\begingroup\$ @tnet what is the bandwidth of the signal that you desire to generate with the dac? When you say DC does this mean it's set and never changes? or is it updated periodically? \$\endgroup\$ – Voltage Spike Aug 21 '18 at 16:00
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Regarding the DNL and INL of a DAC, DNL is the error difference between actual step width and ideal value (1 LSB). INL is the deviation of actual transfer function from the shown straight line (Shown in image below).

I think you have them backwards. I find it easier to look at the equations.

Differential NonLinearity means the difference between the voltage measured on the previous bit vs the bit your looking at now. It is simply a comparison between bits. You are correct in that the DNL needs to be under one to be monotonic. Higher DNL means less glitches in a continuous waveform generation such as a sine wave.

enter image description here
Source: Wikipedia DNL

Integral NonLinearity means from the current value \$ V_{D}\$ to the zero point \$ V_{Zero}\$ (which makes a straight line, and the whole equation forms a variant of y=mx+b or line equation) , and is an absolute measure, If you pick a DAC with lower INL than 1, it will be within 1LSB of the value that you would expect from bottom of the DAC range. INL is for DC or precision applications and knowing exactly what the DAC output is.

$$INL = [\frac{V_D - V_{ZERO}}{V_{LSB-IDEAL}}] - D \space , where \space 0 < D < 2N-1.$$

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  • \$\begingroup\$ "Higher DNL means less glitches in a continuous waveform generation", don't you mean "Lower DNL..." here? \$\endgroup\$ – pipe Dec 4 '18 at 9:16
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If a DAC is having DNL & INL above 1, it's obvious that their SNR would degrade. Your signal reconstruction would have a little more quantization error as DNL & INL are above 1.

You have made the right decision!

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