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I am researching exotic semiconductors for a digital ASIC with a few million logic gates which should run as fast as possible within a $30 million budget. (Specifically, I need to do a single fully-parallel 4096-bit multiplication repeatedly. For more context, I am building an ASIC to compute this Verifiable Delay Function.)

It seems there are semiconductors that perform better than silicon in terms of speed of logic operations, including gallium arsenide, gallium nitride and indium phosphide. My research suggests that these semiconductors are generally used for analogue ASICs as opposed to digital logic, so it is hard to tell which semiconductors are viable for my use case.

Which semiconductor is viable for a digital ASIC with millions of logic gates (say, ~20 million gates) and can provide the fastest performance in terms of speed of logical gates?

Edits in response to comments

  • Budget: Our maximum budget is in the tens of millions of dollars, ~$30 million.
  • Speed: To quantify the speed, we ideally need someone spending $1 billion to be at most 2x faster than us. Notice the Verifiable Delay Function (VDF) is inherently sequential, so lots of parallelism does not help.
  • SiGe process technology: I understood GaAs can give a significant speed bump with respect to SiGe. If 100nm GaAs is faster than 7nm SiGe then size of SiGe is not relevant. As for GaAs, we're only looking to use existing process technology.
  • Pins: We do not need a large number of pins. The reason is there is a single 4096-bit input and a single 4096-bit output per VDF run with 10 minutes of intermediary repeated multiplications spanning 10 minutes. The I/O speed is marginal compared to the multiplication speed.
  • Power and cooling: The ASIC should be runnable by individuals without power supply and cooling that is much more sophisticated than a top-of-the-range GPU.
  • Graphics technology: As I understand, graphics technology is optimised for massively parallel computation. The ASIC we want needs to be optimised for speed of sequential computation, i.e. latency.
  • Obfuscation/reverse engineering: The ASIC will be developed for an open-source project (namely, Ethereum). The ASIC will itself have an open-source circuit design.
  • More context: See these slides that explain the use of the ASIC for a blockchain random number generator.
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    \$\begingroup\$ It mostly comes down to two things: how fast do you need to clock it at? (does it need to run at 1GHz? 10GHz, 100?) and how much do you want to spend? SiGe can hit 5GHz pretty easily even with half a billion gates (the PC CPU overclocking record is nearly 9GHz) and people like Inphy make CMOS chips that can hit 28GHz (as 56Gbit PAM4 uses 28GHz of bandwidth). So... how much speed do you really, really need? \$\endgroup\$ – Sam Aug 20 '18 at 22:55
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    \$\begingroup\$ Please don't say "as fast as possible"...that is absolutely meaningless as an engineering specification. How many gigawatts do you have? How many megadollars do you have? Have you investigated what technologies are used by the graphics processors, since they would seem to be in your ballpark? \$\endgroup\$ – Elliot Alderson Aug 20 '18 at 23:36
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    \$\begingroup\$ Good edits. You mention that a 1 gigadollar spend by a competitor should ideally only double your performance. What's the basis for this hope/estimation? Is there some reason that this would be more of a concern than someone spending their own 30 megadollars for an equal ASIC, or even less to emulate with a single-run device? \$\endgroup\$ – K H Aug 23 '18 at 1:30
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    \$\begingroup\$ Part of the point is obviously to decrease the benefit of additional cores in trying to complete the calculation on time, but you should also evaluate what you can build into an ASIC that would be difficult or laborious to emulate on FPGA architecture, IE a gate structure that by nature wastes a large amount of the FPGA, or that requires more layers of bus or interconnects, some critical component, than are supported. Force your opponent into ASICs of their own to ensure their spend (including reverse engineering) exceeds your own hopefully. \$\endgroup\$ – K H Aug 23 '18 at 1:34
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    \$\begingroup\$ @Randomblue That makes sense. A blockchain random number generator is what I'm reading from your slides. So I guess in order to attack your blockchain an attacker needs to quite significantly outperform, not just match you. Especially because your application is clock speed dependent, you may wish to consider liquid and or sub-ambient cooling. Pushing your asic to its limits for speed in the same type of scenario you'd use to overclock a cpu. It would likely at least be worth testing one of your asics this way once you've built it, just to be sure. \$\endgroup\$ – K H Aug 23 '18 at 10:21
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I'll bet that you don't want raw speed, but speed per dollar, and operations per Joule. In which case, silicon CMOS, because of the huge investment in it, is the 500lb gorilla you should go with.

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I agree with Neil_UK's answer that a "standard" CMOS process is your only choice.

Sure there are technologies to make faster logic, I once designed a frequency divider where the input was working at 30 GHz. That design was using SiGe NPN transistors. However, in that design this frequency divider was only a very small part of the chip. The power consumption of the circuit is so high that if you would make a much more complex digital circuit designed to run at 30 GHz the power dissipation would be far too high making a practical implementation impossible.

My point is that there is always a compromise between speed and power dissipation. Since your circuit requires a lot of gates (it is fairly complex) power dissipation will be the limiting factor.

You see the same in modern CPUs, these contain many cores. When one or only a few cores are used they can run at an increased clock speed. When many cores are used, the clock speed is limited immediately or after a while as the CPU heats up (thermal throttling).

As with CPUs you can get the best performance if you parallelize your design as much as possible, that will result in a lower clock speed at the circuit level but increased overall throughput.

I understand that parallelization isn't what you're looking for but personally I do think you should consider parallelizing as much as possible. Even if you would (try) to get around the power dissipation problem by dividing the circuit over multiple chips running at high speed, that's still parallelization to me. Then you would need to distribute the data signals to the chips, with equal trace lengths, that will introduce delays. That will be a challenge to get right.

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  • \$\begingroup\$ The algorithm is designed to be "inherently sequential" so parallelism does not help past a certain point. How many gates was your 30GHz frequency divider and how much power was it consuming? \$\endgroup\$ – Randomblue Aug 21 '18 at 7:30
  • \$\begingroup\$ Think in the order of less than 100 gates with only about 10 running at 30 GHz, 10 at 10 GHz etc... total power consumption was about 400 mW. That wasn't the fastest SiGe technology so there is some room for improvement. Anyway it is also possible to make CMOS run at 30 GHz or higher, this has been done. Then again only for small circuits as power consumption is the limiting factor. \$\endgroup\$ – Bimpelrekkie Aug 21 '18 at 7:39
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    \$\begingroup\$ To add to this, VLSI is really only done on Si. Most of the exotics are used on very high value low volume applications (relative to Si). The EDA tools, processes etc are not as refined as for Si, and much more expensive. If you're looking for 20M gates, Si is the only practical option given your budget (don't forget a lot of that money is going to be burnt on design and verification...). \$\endgroup\$ – awjlogan Aug 21 '18 at 9:18
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    \$\begingroup\$ I agree with @awjlogan practically all digital design flows (Verilog / VHDL => RTL => layout) are for CMOS processes. It does not mean it cannot be done/made for esoteric processes but doing that will cost you lots of (wo)manpower as cell libraries will need to be made. The design can also be made manually but that also requires more effort. \$\endgroup\$ – Bimpelrekkie Aug 21 '18 at 9:37
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This is building on the other answers so far, but just my thoughts.

Given your budget, and the desire to compete with an entity who's budget is nearly 40X your own, you should not try to use exotics for your application. The major costs in designing this ASIC are going to be:

  • People. I assume you will be paying people to work on this full time as this is not a project that can feasibly be undertaken as an evening project (not withstanding point 2 below). You will need HDL developers, verification engineers, and implementation engineers. All of these are specialised skills with corresponding price tags. In particular, implementation engineers for exotics are (very) low in quantity and high in demand (especially if they're good). Don't expect much change from $1-5M (depending on location) per year.

  • EDA tools. These are expensive, just to license. You also need a lot of them, and multiple seat licenses. HDL compilers, RTL synthesis tools, simulators, layout tools etc. Each license is likely to be on the order of $100K per seat. Don't forget you also need the computing power and infrastructure to run them as well; you will need a pretty powerful cluster.

  • Design. Most tools and process design kits are mature for Si given the volume and revenue for this market. For your exotic, expect less-than-ideal models, especially for cutting edge process nodes. You will need to develop or buy standard cells for your exotic substrate. There will be many fewer than for Si.

  • Manufacture. There are speciality exotic fabs, but they are just that: special. The volumes are low, the wafers are (much) smaller, and costs are much higher (a rough estimate is 100-1000X per mm\$^2\$ compared to Si).

Even after this, there's little guarantee that you'll get the improvement you think you'll get just by running faster. A lot of very clever people have invested a huge amount of time and money in Si, and you'll be re-inventing the wheel for a lot of things (e.g. standard cells, power control etc) and probably be doing it worse. Fabs will often provide standard cells optimised for their process; it would be foolish not to use this. This will erode the advantage of using the exotic in the first place.

Unfortunately, open sourcing the design code doesn't allow you to manufacture the ASIC without a lot of other investment. Now, your $1B competitor can eat a lot of these costs and even if you open source the RTL, they can do the rest of the things which you simply can't open source. For example, semiconductor fabs are very cagey about releasing their in-house process models. You should do a very thorough audit as to the advantage of open sourcing in this case; manufacture simply doesn't scale in the same way software distribution does so the pros and cons are very different.

To answer your questions:

  1. Budget limits everything (of course). Given the disparity to your hypothetical competitor, $30M would be much better spent on high quality people to develop a good architecture rather than trying to get "free" performance from the materials and process used. As my comments above hopefully illustrate, this "free" performance will be anything but free!

  2. Good architecture will mitigate a lot of the advantage of going to an in-house exotics design. There is still potential for scaling in GaAs and other exotics. This may become relevant in the (near?) future - keep your powder dry to take advantage of that.

  3. SiGe is closer to Si, so you may be able to use this more freely, although it will still be more expensive than Si. GaAs is more specialised, and is usually used for it's high ft in RF designs where area cost is less of a concern. Going from 100 nm to 10 nm gives you (to a first order) you 100X more transistors to implement your excellent architecture. Of course, architectural improvement usually scales as \$\sqrt{N_\mathrm{transistors}}\$, so probably around 10X performance gain overall. Bear in mind though, that even $1B is nowhere near enough to push a fully new process through, so the chances are your competitor will still be using Si.

  4. SERDES for 4096 bits is a lot of registers - this is going to cost a lot of power and area for no performance benefit on your exotic wafer. Given you can fit whole processors in fewer than 4096 registers (let alone 8192), this illustrates the issue there. Area is much cheaper on Si.

  5. Going to smaller transistors means higher power density, hence more need for power control, i.e. bits that are turned off (dark silicon). A lot of work has gone into analysing and reducing power consumption while maintaining acceptable performance. A critical factor is your expected activity. Will it be working full throttle 24/7, or will it be periodic? This will make a big difference to your design.

  6. A $1B competitor has no care about obfuscation if the reward is high enough. Don't be hubristic in thinking your design is the perfect implementation.

To summarise, you should spend your money on the people and tools that develop your architecture and algorithm (don't forget that!). This is likely to provide the best return for your relatively constrained budget by leveraging the massive investment in both tools and process for Si. Simply using a faster material is highly unlikely to give you the improvement it seems on paper by raising the clock rate, given all the other steps in designing and making an ASIC.

Personally, I would target a "cheap" Si node (probably something like 22 or 28 nm) to get your design up and running. If it's successful, you can use the scaling benefits to go to smaller (and more expensive) nodes, leveraging the work you've done already and the work done by the fabs. In the interim, as you are developing an ASIC, you can push the operating conditions wider as well, as compared to a CPU/GPU which has to work across a huge and unknown range of conditions. For example, you can specify the cooling equipment that should be used. This will further erode any advantage by going to higher performance materials.

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  • \$\begingroup\$ Thank you for this detailed answer :) Would you agree that SiGe is the less exotic of the non-Si semiconductors, and that SiGe is probably within the realm of our budget? Do you have any intuition as to whether 90nm SiGe would perform better or worse than 22nm Si? What about 7nm Si? \$\endgroup\$ – Randomblue Aug 23 '18 at 15:14
  • \$\begingroup\$ @Randomblue It's very hard to say, as a 22 nm Si FET isn't just a 90 nm Si FET shrunk 10X. There's huge amounts of materials engineering (including SiGe channels!) and solid state physics involved. A difficulty in going to 7 nm is the power density; not good for full time full loading (happy to expand answer). SiGe may be in your manufacturing budget, but with the factors in my answers I think it would be outside your overall budget, given how much cheaper/mature Si CMOS is and how many gains you can get elsewhere. \$\endgroup\$ – awjlogan Aug 23 '18 at 15:53
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I looked into these exotic materials as well for our next-generation PoW mining ASICs and, as others have stated, they are just not ready for volume production yet.

For about $20 million though, you can get a design and masks at 7nm, which, as you likely know, is the best Si process currently available for volume production. Getting fab time for 7nm is quite challenging though. In fact, getting fab time for 14nm or under often requires waiting months or years depending on the process node and specific fab.

In addition, fabs are going to require that you show them that you have the financial ability to follow through with a large enough wafer order to make it worth their while. This makes a 7nm project, including wafers, come in somewhere around $50-100 million depending on the fab's mask cost, cost per wafer, and minimum number of wafers. That's before building the hardware to contain the ASICs, which will typically double the costs. This can vary a lot though based on the number of ASICs required in each unit, power requirements, cooling requirements, etc.

The Obelisk Launchpad program is intended for projects just like this that require transparency and openness. In fact, Launchpad requires that the resulting ASIC design be open sourced. By default, the Launchpad process is oriented around a 22nm design, but that can easily be changed to something else. Disclaimer: I work for Obelisk.

You may also find this blog post on The State of Cryptocurrency Mining useful to understand more about the ASIC manufacturing process.

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