# Can N-Channel MOSFETs safely discharge capacitors?

Can 3 ganged 120 A rated N-Channel MOSFETs discharge a charged cap dumping 300 A?

Will the FETs just explode or can they repeatedly discharge the cap?

What specific ratings and characteristics are important to determine if a FET is up to the task?

Granted the FET's Vds voltage would slightly exceed the cap voltage rating.

• How are you controlling it to 300A – JonRB Aug 21 '18 at 20:13
• And 300A for how long? A microsecond or a second? How often will it need to operate? 50khz or twice/minute? How many Farad and how many volts? If it is a multiple capacitor bank, include the values of the individual capacitors and the voltage/rating you expect it to perform at? – K H Aug 22 '18 at 1:31
• It depends on all the details. ALL the details. What kind of capacitors? Which MOSFET? I assume it is not 300A continuous, but more like 300 peak? Ideally, you would build the circuit, then test it. You would measure Vds and Id simultaneously on an oscilloscope to figure out how many joules the FET is absorbing, and then take a look at the pulse ratings of the scope. It is a tricky business. You might consider using an SCR instead. – mkeith Aug 22 '18 at 3:24
• *pulse rating of the FET – mkeith Aug 22 '18 at 3:36
• I actually was hoping to discharge 80v capacitors 130A peak @ 10mS duration pules 2 per sec for a few minutes. It turns out MOSFETs are very poor candidates for this spec. – user33915 Aug 22 '18 at 3:52

Weather they can handle the discharge depends on a few things.
1) How much energy is in the capacitors. E = 0.5 * C * V^2

2) Where do you expect the energy will be dissipated during the short. And what fraction of the total energy is going into the FET. Energy may be dissipated in the following places.

a) In the internal ESR of the capacitors.
b) In the drain source resistance of the FET
c) In an external series resistor put in the circuit to absorb energy during the short
d) In the wiring resistance

3) What pulsed energy can the FET handle. You can usually find this in the Safe Operating Area graph for the FET.

For example...
C = 1mF
V = 30V
ESR = 15mOhms (from capacitor datasheet)
Therefore...
E = 0.5 * 1mF * 30V * 30V = 450mJ

Lets say that the datasheet for the FET lists Rds_on = 10mOhms.
Lets also say that we have 5mOhms of wiring resistance.
The peak curent would then be 30V / (10mOhms + 5mOhms + 15mOhms) = 1000A.

Lets say that the FET datasheet safe operating area graph says that the FET can handle 1000A with Rds = 30V for 10us. The pulsed energy rating would then be 0.3J. If the graph didn't say it could handle a 1000A pulse we would need to add a series resistor.

The energy dissipated in the FET is 450mJ * 10mOhms / (10mOhms + 5mOhms + 15mOhms) = 150mJ.

So in this case the FET would survive because 150mJ is less than 0.3J.

Lets try another example...
C = 1mF
V = 50V
ESR = 15mOhms (from capacitor datasheet)
Therefore...
E = 0.5 * 1mF * 30V * 30V = 1.25J

Lets say that the datasheet for the FET lists Rds_on = 10mOhms.
Lets also say that we have 5mOhms of wiring resistance.

The peak curent would then be 50V / (10mOhms + 5mOhms + 15mOhms) = 1666A.

Lets suppose that the FET datasheet says the FET can't handle more than 100A peak. Therefore we add a 0.5 ohm resistor in series to limit the current.

The peak current is now 50V / (10mOhms + 5mOhms + 15mOhms + 0.5 ohms) = 94.34A.

Lets also say that the SOA graph says the FET can handle 100A at 50V for 100us. 100A * 50V * 100us = 0.5J.

The energy dissipated by the FET during the discharge is...

1.25J * 10mOhms / (10mOhms + 5mOhms + 15mOhms + 0.5 ohms) = 23mJ.

In this case adding the series resistor greatly reduced the energy dissipated by the FET. Since 23mJ is much less than the 0.5J rating the FET in this example would survive.

One thing to point out in your specific case is that you can't depend on the Rds_on of the FETs being matched. That is you can't assume that each FET will share current evenly. Instead of 100A, 100A, 100A, you could get 70A, 130A, 100A or similar. You can only guarantee that the current sharing is even if you add some external resistance that is significantly higher than the FETs Rds_on.

• Instead of resistors why not add more FETs? Ganging more FETs FORCES current to be shared, even if it were not shared equally it still lowers the power each FET has to conduct. Wouldn't this be a method to avoid resistors? Also, RDSon is increased with thermal rise which proper thermal considerations such as symmetric layout and symmetric ventilation would prevent. Other than that you gave the most practical, easy to understandable and actually the simplest approach I have found for the determination of FETs handling cap energy dumping capabilities. Greatly appreciated. – user33915 Aug 22 '18 at 3:06

Will the FETs just explode or can they repeatedly discharge the cap?

They will explode if they overheat from the current. Maybe not explode, but a low impedance source can cause things to overheat really really quick, and when they do bad things could happen.

What specific ratings and characteristics are important to determine if a FET is up to the task?

The thermal junction rating and how much power is being dissipated in the part. One problem you may have is the transition time, with that much current being sourced there will be a short period of time where the part will have high resistance as it turns on. During this period the part will heat up the most (assuming you have a very low rdson or the lowest resistance the device can achieve when the gate voltage or Vgs is high). I

The other thing that will affect how much current is being sourced is the capacitors series resistance and inductance (ESR and ESL). I would recommend simulating the design in spice to ballpark the thermal numbers.

I would suggest that you will NOT be able to use 3 * 120 to attempt to draw 300A discharge current from a capacitor.

There will be differences between the devices and any reasonable attempt to balance the current across those devices will simply limit the maximum current drawn.

To understand the problem at such high currents you should read some of the datasheets and application notes from IXYS.

Consider firstly a single device able to sustain 360A, such as the IXYS IXFK360N15T2. First thought is that this might be up to the task BUT then you have to consider the limitations:

The device CAN support 360A, but not continuously (In fact it can support short pulse currents up to an amazing 900A). From the datasheet wee see that the bonding and leadframes can only support 160A. In addition energy density within the channel will eventually lead to local melting and failure. The real practical capability of the device is clearly shown in the SOA graph below: As the current increases the VDD will increase and the lead limits, bond limits and chip limits mean you have to reduce the time that you can sink this current.

For example, if you are discharging a small 0.1uf capacitor from say 100 volts, it will discharge rapidly, but if you try to discharge a supercap array from 100 volts, then you simply be generating blue light.

You didn't specify the capacitor or the voltage so it's hard to offer advice, but you can think of the discharge circuit as simply the capacitor ESR and the FET RDS(on) as the limit of the problem.

If the capacitor ESR is close to the RDS(on), then approximately half the capacitor voltage will appear as VDD. From there it's simply an RC problem ...how long and at what rate will the VDD drop.
Too long to discharge and things will start to melt, which is impressive and demands attention when it happens ...but not very practical.

• If economics were no issue then can ganging a vast amount would at least in theory achieve cap discharges with MOSFETs even without heatsinks and balance resistors? Also this is quite impractical as the compnent value would likely be enormous. – user33915 Aug 22 '18 at 3:08
• @user9762541 ….what is impractical? ...and what component value are you talking about? – Jack Creasey Aug 22 '18 at 3:37
• Making an enormous FET gang to handle enourmous pulses even without heatsinks. – user33915 Aug 22 '18 at 3:51
• @user9762541 paralleling multiple FETs is always problematic. At the simplest end of the scale you are adding lots of Gate capacitance together which makes rapid turn on difficult, then you have uneven current distribution across devices. Will it work ...yes, after a fashion, but not a good design strategy IMO. – Jack Creasey Aug 22 '18 at 4:11